
Ordering number : EN
*
5391
41596HA (OT) No. 5391-1/7
Overview
The LC89975M is a lower-cost PAL-Format CCD delay
line based on the LC89970M, with the sizes of chip and
package miniaturized and the external parts count reduced.
Features
5 V single-voltage power supply
On-chip 3
×
PLL circuit for 3·fsc operation from an fsc
(4.43 MHz) input
Supports PAL/GBI and 4.43 NTSC systems, selected by
a control pin input
Includes an on-chip comb filter for chrominance signal
crosstalk exclusion. This adjustment-free circuit
provides high-precision comb characteristics.
Peripheral circuits included on chip to allow operation
with minimal external circuits.
Positive-phase signal input, positive phase signal output
(luminance signal)
Functions
CCD shift register (for chrominance and luminance
signals)
CCD drive circuit
Circuit for switching the number of CCD stages
CCD signal addition circuit
Auto-bias circuit
Sync tip clamping circuit (luminance signal)
Center bias circuit (chrominance signal)
Sample-and-hold circuit
PLL 3
×
circuit
3·fsc clock output circuit
RD voltage generation step-up circuit
Package Dimensions
unit: mm
3111-MFP14S
Preliminary
SANYO: MFP14S
[LC89975M]
LC89975M
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
PAL-Format Delay Line
NMOS + CCD
Specifications
Absolute Maximum Ratings
at Ta = 25°C
Recommended Conditions
at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
V
DD
Pdmax
–0.3 to +6.0
V
Allowable power dissipation
250
mW
Operating temperature
Topr
–10 to +60
°C
Storage temperature
Tstg
–55 to +150
°C
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
V
DD
V
CLK
F
CLK
V
IN-C
V
IN-Y
4.75
5.00
5.25
V
Clock input amplitude
300
500
1000
mVp-p
Clock frequency
Sine wave
—
4.43361875
—
MHz
Chrominance signal input amplitude
—
350
500
mVp-p
Luminance signal input amplitude
—
400
572
mVp-p