參數(shù)資料
型號(hào)： LC89052TA-E
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO24
封裝： 0.225 INCH, TSSOP-24
文件頁(yè)數(shù)： 25/42頁(yè)
文件大?。?/td> 224K
代理商： LC89052TA-E
LC89052TA-E
No.7457-31/42
9.6.2 Details of write data
Table 9.5 Input Register Function Settings 1: System Settings (0xE8)
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
MCKHFO
PLLCK1
PLLCK0
PLLOPR
PDOWN1
PDOWN0
0
SYSRST
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI8
XISEL3
XISEL2
XISEL1
XISEL0
OCKSEL
AMPCNT
AMPOPR
0
SYSRST:
System reset
0: No reset performed (initial value)
1: Reset all circuits other than the command registers.
PDOWN[1:0]:
Low power mode settings (Only specific functions are enabled.)
00: Normal operation (initial value)
01: Only the oscillator amplifier is enabled.
10: Only the oscillator amplifier and the output clock divider are enabled.
11: Reserved
PLLOPR:
PLL (VCO) operate/stop setting
0: Operate (initial value)
1: Stop
PLLCK[1:0]:
Clock frequency setting in the PLL locked state
00: 256fs (initial value)
01: 384fs
10: 512fs
11: (512/2)fs = 256fs
MCKHFO:
Frequency setting of CKOUT output clock
0: 1/1 output (initial value)
1: 1/2 output
It is possible to maintain clock continuity when switching from the 512fs setting with PLLCK[1:0] = "10" to the
(512/2) fs setting with PLLCK[1:0] = "11", and switching vice versa without entering the PLL lock error state.
For systems that must minimize power consumption such as portable equipment, we recommend the PLLCK[1:0] =
"00" (256fs) setting. For systems that require improved performance such as AV amplifiers, we recommend the
PLLCK[1:0] = "10" (512fs) or PLLCK[1:0] = "11" (512/2fs) setting.
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參數(shù)描述
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LC89052THS-E 制造商:ON Semiconductor 功能描述:AUDIO I/F RECEIVER
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LC89056W-E 功能描述:音頻發(fā)送器、接收器、收發(fā)器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類(lèi)型:I2C, SPI 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝:
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