參數(shù)資料
型號(hào): LC8904
廠商: Sanyo Electric Co.,Ltd.
英文描述: Digital Audio Interface Receiver
中文描述: 數(shù)字音頻接口接收器
文件頁數(shù): 4/20頁
文件大?。?/td> 322K
代理商: LC8904
Pin Functions
No. 5014-4/20
LC8904Q
No.
Symbol
I/O
Function
1
DOUT/V
O
EIAJ data and validity flag output
2
EMPHA
O
Emphasis monitor output (High: emphasis applied)
3
RC1
I
CR oscillator input
4
RC2
O
CR oscillator output
5
CCB/SUB
I
Microprocessor interface selection input (High: CCB, low: SUB)
6
DGND
Digital system ground
7
CLKMD
I
Clock output switching (High: 256fs, low: 128fs)
8
CLK
I
Clock switching input (High: 512fs, low: 384fs)
9
TEST1
I
Test pin (Must be tied low during normal operation.)
10
TEST2
I
Test pin (Must be tied low during normal operation.)
11
XMODE
I
Reset input
12
DV
DD
NC
Digital system power supply
13
No connection
14
AV
DD
R
Analog system power supply
15
I
VCO oscillator band adjustment input
16
AGND
Analog system ground
17
VIN
I
VCO free-running frequency setting input
18
VCO
O
PLL low-pass filter connection
19
DV
DD
SBSY
Digital system power supply
20
O
CD subcode interface: block sync output
21
PW
O
CD subcode interface: data output
22
SFSY
O
CD subcode interface: frame sync output
23
SBCK
I
CD subcode interface: data read shift clock input
24
DGND
Digital system ground
25
DV
DD
XIN
Digital system power supply
26
I
Crystal oscillator input
27
XOUT
O
Crystal oscillator output
28
CLKOUT1
O
VCO and crystal oscillator clock output
29
CLKOUT2
O
256fs or 128fs clock output (selected by CLKMD)
30
ERROR
O
Error mute output
31
DGND
Digital system ground
32
SUB1
O
Sampling frequency monitor output
33
SUB2
O
Sampling frequency monitor output
34
BCLK
O
Bit clock output
35
DATAOUT
O
Audio data output
36
LRCK
O
L/R clock output (High: left channel, low: right channel)
37
LD/DQSY
O
Microprocessor interface: subcode Q data sync output
38
SRDT
O
Microprocessor interface: data output when CCB/SUB is low (3-state output)
39
DO
O
Microprocessor interface: data output when CCB/SUB is high (High-level open drain output)
40
DI/SWDT
I
Microprocessor interface: data input
41
CE/XLAT
I
Microprocessor interface: chip enable/latch input
42
CL/SCLK
I
Microprocessor interface: clock input
43
DV
DD
DIN1
Digital system power supply
44
I
Data input with built-in amplifier
45
DIN2
I
Data input with built-in amplifier
46
DIN3
I
Data input with built-in amplifier
47
DIN4
I
Data input with built-in amplifier
48
DGND
Digital system ground
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