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參數(shù)資料
| 型號： | LC8900KQ |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Digital Audio Interface Receiver |
| 中文描述： | 數(shù)字音頻接口接收器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 146K |
| 代理商： | LC8900KQ |
DATA
(1) The relationship between the data input pins and the data select pins are shown in the table below.
Each input pin has an internal amplification circuit. Therefore the signal with the amplitude of 400 m V
P-P
up to
V
DD
+0.3 V can be input to this LSI chip. However, in the case of coaxial cable or optical module input the application
will change as the sample application circuit shown later.
Connect to the unused input pin to the GND or V
DD
.
(2) The relationship between the OUTMODE pin and the two output data formats is shown in the table below.
IF an error is detected in an input data, that input data is not output. Instead, the previous data will be output.
The data output is synchronized with falling edge of the bit clock.
IF the PLL is in the Lock state, the 384 Fs or 256 Fs clock that is synchronized with the output data will be output.
Note that the duty is of the 256 Fs clock is 'H:L = 2:1'. It is not 'H:L = 1:1'.
Sub Codes
The sub code output consists of the copy inhibit signal, emphasis mode signal, sampling frequency signal, validity flag
signal and user’s bit. The table below details these sub code outputs.
Clock Modes
The control clock is specified by the VCO. The VCO has two modes: self oscillation mode and PLL mode as shown
below.
When the STOP pin is changed to the high level, the PLL functional circuit block stops its operation and the entire
circuit operation is then forced to stop. The entire circuit will start the normal operation again when the STOP pin is
changed to the low level.
If the LOCK operation is not activated in a certain fixed time period after the PLL enters the lock-up state:
Reinitialize the PLL functional circuit block to active the lock-up mode. This should be done to prevent the PLL lock
error.
No. 4128-7/12
LC8900KQ
COPY inhibit signal
COPY pin level = high:Copy not inhibited.
COPY pin level = low:Copy inhibited.
Emphasis mode signal
EMPHA pin level = high:Emphasis mode.
EMPHA pin level = low:Non emphasis mode.
BSA pin level = high:32 kHz sampling frequency
Sampling frequency
CD pin level = high:44.1 kHz sampling frequency
BSB pin level = high:48 kHz sampling frequency
Validity flag signal
This signal is output from the V pin in sub frame unit.
User’s bit
This signal is output from the U pin in sub frame unit.
Self oscillation mode
XMODE pin level=low
The VCO continues its oscillation according to the VIN pin potential. BCLK,
LRCK, and FS256 clocks are not effective.
No data input
The VCO continues its oscillation according to the VIN pin potential. FS384,
BCLK, LRCK, and FS256 clocks output.
PLL mode
Data input with the XMODE pin level=high
The PLL block and the entire circuit are in the normal operation state.
SEL1
SEL2
DOUT
DIN1
L
L
DIN1 data output
DIN2
L
H
DIN2 data output
DIN3
H
L
DIN3 data output
DIN4
H
H
low level signal output
(fixed level output)
OUTMODE pin
H
20-bit LSB first data output format
L
16-bit MSB first data output format
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相關代理商/技術參數(shù) |
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| LC8900Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| LC8901 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8901Q | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8902 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8902Q | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
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