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參數(shù)資料
| 型號： | LC8900KQ |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Digital Audio Interface Receiver |
| 中文描述： | 數(shù)字音頻接口接收器 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 146K |
| 代理商： | LC8900KQ |
Pin Functions
No. 4128-3/12
LC8900KQ
Pin No.
Pin Name
I/O Type
Functional Description
1
DOUT
O
Input data output pin. However, its output is fixed at the low level if the DIN4 input pin is selected.
2
RC1
I
RC oscillation pin
3
RC2
O
RC oscillation pin
4
SEL1
I
Input pin select pin
5
SEL2
I
Input pin select pin
6
LPF
I
High level = LPF time constant select mode. low level = LPF time constant fixed mode. Fixed to high in most cases.
7
STOP
I
High = level:Forces the VCO operation to stop. Fixed to low in most cases.
I
Output data format select pin.
8
OUTMODE
High = 20-bit LSB first data format.
Low = 16-bit MSB first data format
9
TEST2
I
Test pin:Connected to the DGND in most cases.
10
XMODE
I
Input pin to start the PLL operation immediately after the LSI chip is powered on.
11
DV
DD
AV
DD
R
Digital power supply
12
Analog power supply
13
I
VCO oscillation bandwidth adjust pin
14
AGND
Analog ground
15
Vin
I
VCO self oscillation frequency setting pin
16
VCO
O
PLL LPF pin
17
DGND
Digital Ground
18
TEST1
I
Test pin:Connected to the DGND in most cases.
19
V
O
Validity flag output pin
20
FS256
O
256 Fs clock output pin
21
FS384
O
384 Fs clock output pin
22
DV
DD
BCLK
Digital Power Supply
23
O
Bit clock output pin
24
DATAOUT
O
Audio data output pin
25
LRCK
O
L/R clock output pin, Lch = high, Rch = low
26
EMPHA
O
Emphasis control (on/off) output pin:High = emphasis mode. Low = none-emphasis mode.
27
LOCK
O
PLL lock state output pin:High = PLL locked state. Low = PLL unlocked state.
28
ERROR
O
Input data error detect signal output:High = error detected.
29
COPY
O
Copy information output pin
30
BSA
O
Input data sampling frequency indication:High = 2 kHz.
31
CD
O
Input data sampling frequency indication:High = 44.1 kHz.
32
BSB
O
Input data sampling frequency indication:High = 48kHz.
33
U
O
User’s bit output pin
34
DO
O
Microcontroller interface output pin
35
DI
I
Microcontroller interface input pin
36
CE
O
Microcontroller interface chip enable input pin
37
CL
O
Microcontroller interface clock input pin
38
MODE
I
Microcontroller interface control input:High = microcontroller interface active mode.
Low = microcontroller interface inactive mode.
39
DV
DD
DIN1
Digital power supply
40
I
Data input pin
41
DIN2
I
Data input pin
42
DIN3
I
Data input pin
43
DIN4
I
Data input pin
44
DGND
Digital ground
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| LC8902Q | Digital Audio Interface Receiver(數(shù)字音頻接口接收器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC8900Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| LC8901 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8901Q | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8902 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8902Q | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
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