參數資料
型號: LC87F5164A
廠商: Sanyo Electric Co.,Ltd.
英文描述: 8-Bit Single Chip Microcontroller with 64KB(65535 ×8 bits) FEPROM and 1024 Byte(1024 ×8 bits) RAM On Chip(8位單片微控制器(帶片上64K(65535 ×8 bit)字節(jié)閃速EPROM和1024(1024 ×8 bits)字節(jié)RAM))
中文描述: 8位單片機微控制器的64KB(65535 × 8位)FEPROM和1024字節(jié)(1024 × 8位)片上的RAM(8位單片微控制器(帶片上64K的(65535 × 8位)字節(jié)閃速存儲器和1024(1024 × 8位)字節(jié)的RAM))
文件頁數: 18/28頁
文件大?。?/td> 787K
代理商: LC87F5164A
LC87F5164A
18/28
5. Parallel Input/ Output Characteristics at Ta=-20
°
C to +70
°
C, VSS1=VSS2=VSS3=0V
Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format.
Please refer to figures 8 and 9 for parallel output timing waveforms.
Ratings
typ.
1
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5 - 5.5
min.
max.
unit
Write cycle, Read
cycle
Address set-up
time
tC(1)
tCYC
tsA(1)
WR
(PA3), PB0-PB7
RD
(PA4), PC0-PC7
RD
(PA4), PC0-PC7
4.5 - 5.5
1/3tCYC
-30ns
tsA(2)
From address set-up
until control signal
changes
4.5 - 5.5
2/3tCYC
-30ns
1/6tCYC
thA(1)
RD
(PA4), PC0-PC7 From change of
RD
until address change
4.5 - 5.5
tCYC
& ns
Address hold time
thA(2)
WR
(PA3), PC0-PC7 From change of
WR
until address change
From change of RS,
CS
until change in
WR
from change of RS
until change in
RD
4.5 - 5.5
5
ns
tsRS(1)
WR
RS(PA5),
CS
(PAX)
RD
(PA4), RS(PA5)
(PA3),
4.5 - 5.5
1/6tCYC
-15ns
tsRS(2)
4.5 - 5.5
1/6tCYC
-15ns
1/3tCYC
-15ns
1/3tCYC
-15ns
RS set-up tie
tsRS(3)
RD
(PA4), RS(PA5)
4.5 - 5.5
tsCS(1)
RD
(PAX)
(PA4),
CS
From change in
CS
until change in
RD
From change in
CS
until change in
WR
4.5 - 5.5
CS
set-up time
tsCS(2)
WR
(PAX)
(PA3),
CS
4.5 - 5.5
2/3tCYC
-15ns
tCYC
& ns
thRS(1)
WR
(PA3), RS(PA5) From change in
WR
until change in RS
From change in
RD
until change in RS,
CS
4.5 - 5.5
0
ns
thRS(2)
RD
(PA4), RS(PA5),
CS
(PAX)
4.5 - 5.5
1/6tCYC
tCYC
& ns
RS
hold time
thRS(3)
RD
(PA4), RS(PA5),
CS
(PAX)
RD
(PA4), RS(PA5) From change in
RD
4.5 - 5.5
0
ns
thCS(1)
until change in
CS
4.5 - 5.5
1/6tCYC
tCYC
& ns
CS
hold time
thCS(2)
WR
(PA3), RS(PA5) From change in
WR
until change in
CS
4.5 - 5.5
0
ns
tWRH(1)
WR
(PA3)
4.5 - 5.5
1/6tCYC
-5ns
2/3tCYC
-5ns
1/6tCYC
-5ns
1/3tCYC
-5ns
1/6
tCYC
2/3
tCYC
1/6
tCYC
1/3
tCYC
WR
‘H’ pulse width
tWRH(2)
WR
(PA3)
4.5 - 5.5
tWRL(1)
WR
(PA3)
4.5 - 5.5
WR
‘L’ pulse width
tWRL(2)
WR
(PA3)
4.5 - 5.5
tCYC
& ns
(Continued)
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