參數(shù)資料
型號(hào): LC87F2932AU-CD-E
廠商: ON Semiconductor
文件頁(yè)數(shù): 23/29頁(yè)
文件大小: 0K
描述: IC MCU 8BIT 32K FLASH 64TQLP
標(biāo)準(zhǔn)包裝: 250
芯體尺寸: 8-位
速度: 12MHz
連通性: SIO,UART/USART
外圍設(shè)備: PWM,WDT
輸入/輸出數(shù): 59
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: *
包裝: *
LC87F2932A
No.A1210-3/29
UART
Full duplex
7/8/9 bit data bits selectable
1 stop bit (2-bit in continuous data transmission)
Built-in baudrate generator
AD Converter: 8 bits
× 13 channels
PWM: Multifrequency 12-bit PWM
× 2 channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
Watchdog Timer
External RC watchdog timer
Interrupt and reset signals selectable
Clock Output Function
1) Outputs clock with a frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock of the system clock
2) Outputs clock of the subclock
Interrupts
26 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/ BT0/BT1/DHMSC
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
T1L/T1H/INT7
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/T4/T5/PWM2, PWM3
Priority levels X > H > L
Of interrupts of the same level, the one with the smallest vector address takes precedence.
IFLG (List of interrupt source flag function)
1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the table
above).
Subroutine Stack Levels: 1024 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
16 bits × 8 bits
(5 tCYC execution time)
24 bits × 16 bits
(12 tCYC execution time)
16 bits ÷ 8 bits
(8 tCYC execution time)
24 bits ÷ 16 bits
(12 tCYC execution time)
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