參數(shù)資料
型號: LC876748A
廠商: Sanyo Electric Co.,Ltd.
元件分類: 8位微控制器
英文描述: 8-Bit Single Chip Microcontroller
中文描述: 8位單片機(jī)微控制器
文件頁數(shù): 13/26頁
文件大小: 1099K
代理商: LC876748A
LC876764A/48A
13/26
2. Recommended operating range / Ta=-30°C to +70°C, VSS1=VSS2=0V
Limits
min.
4.5
Parameter
Symbol
Pins
Conditions
VDD
[V]
typ.
max.
6.0
unit
V
Operating
supply voltage
range
Hold voltage
VDD(1)
VDD1=VDD2=VDD3
=VDD4
0.294μs
Tcyc
200μs
VHD
VDD1
RAM and the
register data are
kept in HOLD
mode.
Output disable
2.0
6.0
VIH(1)
Port 0,3: CMOS
output option
Port 8
Port 0,3: N-ch open
drain output
Port 1
Port71,72,73
P70 port input/
interrupt
S16 to S51
4.5–6.0 0.3VDD
+0.7
VDD
VIH(2)
Output disable
4.5–6.0 0.3VDD
+0.7
13.5
VIH(3)
Output disable
4.5–6.0 0.3VDD
+0.7
VDD
VIH(4)
Output P-channel
Tr. OFF
Output disable
Output disable
4.5–6.0 0.3VDD
+1.0
VDD
VIH(5)
VIH(6)
P70 Weak signal input
Port 70
Watchdog timer
XT1, XT2, CF1, RES
4.5–6.0 0.75VDD
4.5–6.0 0.9VDD
VDD
VDD
Input high
voltage
VIH(7)
4.5–6.0 0.75VDD
VDD
VIL(1)
Port 0,3: CMOS
output option
Port 8
Port 0,3: N-ch open
drain output
Port 1
Port 71,72,73
P70 port input
/interrupt
S16 to S51
Output disable
4.5–6.0
VSS
0.15VDD
+0.4
VIL(2)
Output disable
4.5–6.0
VSS
0.15VDD
+0.4
0.1VDD
+0.4
VIL(3)
Output disable
4.5–6.0
VSS
VIL(4)
Output P-channel
Tr. OFF
Output disabled
4.5–6.0
-35
0.2VDD
VIL(5)
Port 87 weak signal
input
Port 70
Watchdog timer
XT1,XT2,CF1, RES
4.5–6.0
VSS
0.25VDD
VIL(6)
Output disabled
4.5–6.0
VSS
0.8VDD
-1.0
0.25VDD
200
10
Input low
voltage
VIL(7)
t
CYC
4.5–6.0
4.5–6.0
4.5–6.0
VSS
0.294
0.1
Operation
cycle time
External
system clock
frequency
μs
CF2 open circuit
system clock
divider set to 1/1
external clock
DUTY = 50±50%
CF2 open circuit
system clock
divider set to 1/2
Continued
fEXCF(1) CF1
4.5–6.0
0.2
20
MHz
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