參數(shù)資料
型號： LC875064B
廠商： Sanyo Electric Co.,Ltd.
英文描述： 8-Bit Single Chip Microcontroller with 64K-Byte(65535 ×8 bits) EPROM and 2048-Byte(2048 ×8 bits) RAM On Chip(8位單片微控制器（帶片上64K（65535 ×8 bit）字節(jié)EPROM和2048(2048 ×8 bits)字節(jié)RAM）)
中文描述： 8位單片機(jī)微控制器64K的字節(jié)（65535 × 8位）存儲器和2048字節(jié)（2048 × 8位）片上的RAM（8位單片微控制器（帶片上64K的（65535 × 8位）字節(jié)存儲器和2048（2048 × 8位）字節(jié)的RAM））
文件頁數(shù)： 15/26頁
文件大小： 762K
代理商： LC875064B
LC875064B/56B/48B
15/26
4. Serial Input/Output Characteristics at Ta=-20
°
C to +70
°
C, VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
2.5 - 6.0
min.
2
max.
unit
Cycle
t
SCK
(1)
t
SCKL
(1)
t
SCKLA
(1)
t
SCKH
(1)
t
SCKHA
(1)
t
SCK
(2)
t
SCKL
(2)
1
Low level
pulse width
1
1
High level
pulse width
SCK0(P12)
Refer to figure 6
3(SIO0)
2
Cycle
Low level
pulse width
High level
pulse width
Cycle
1
I
t
SCKH
(2)
SCK1(P15)
Refer to figure 6
2.5 - 6.0
1
t
SCK
(3)
t
SCKL
(3)
t
SCKLA
(2)
4/3
t
CYC
Use pull-up resistor
(1k
) when output
is open drain.
Refer to figure 6
SCK0(P12)
SIO0
1/2
Low level
pulse width
3/4
t
SCKH
(3)
t
SCKHA
(2)
1/2
High level
pulse width
SCK0(P12)
SCK0(P12)
SIO0
2.5 - 6.0
2
tSCK
Cycle
t
SCK
(4)
t
SCKL
(4)
2
t
CYC
Low level
pulse width
High level
pulse width
Data set-up
time
Data hold
time
Output delay
time
1/2
S
O
t
SCKH
(4)
SCK1(P15)
CMOS output option
Refer to figure 6
2.5 - 6.0
1/2
tSCK
4.5 - 6.0
0.03
tsDI
2.5 - 6.0
0.03
4.5 - 6.0
0.03
S
thDI
SB0(P11),
SB1(P14),
SI0,
SI1
Data set-up to
SI0CLK
Refer to figure 6
2.5 - 6.0
0.03
4.5 - 6.0
1/3tCYC
+0.05
S
tdD0
SO0(P10),
SO1(P13),
SB0(O11),
SB1(P14)
Data set-up to
SI0CLK
When port is open
drain: Time delay
from SI0CLK trailing
edge to the SO data
change.
Refer to figure 6
2.5 - 6.0
1/3tCYC
+0.05
μ
s
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