No. 7135-3/24
LC75863E, 75863W
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Hysteresis
V
H
V
DET
I
IH
I
IL
V
IF
R
PD
I
OFFH
V
OH
1
V
OH
2
V
OH
3
V
OH
4
V
OL
1
V
OL
2
V
OL
3
V
OL
4
V
OL
5
V
MID
1
V
MID
2
V
MID
3
V
MID
4
V
MID
5
fosc
CE, CL, DI, KI1 to KI5
0.1 V
DD
V
Power-down detection voltage
2.5
3.0
3.5
V
Input high level current
CE, CL, DI: V
I
= 6.0V
CE, CL, DI: V
I
= 0V
KI1 to KI5
5.0
μA
Input low level current
–5.0
μA
Input floating voltage
0.05 V
DD
V
k
μA
Pull-down resistance
KI1 to KI5: V
DD
= 5.0V
DO: VO = 6.0V
50
100
250
Output off leakage current
6.0
KS1 to KS6: I
O
= –500μA
P1 to P4: I
O
= –1mA
S1 to S25: I
O
= –20μA
COM1 to COM3: I
O
= –100μA
KS1 to KS6: I
O
= 25μA
P1 to P4: I
O
= 1mA
S1 to S25: I
O
= 20μA
COM1 to COM3: I
O
= 100μA
DO: I
O
= 1mA
COM1 to COM3: 1/2bias, I
O
= ±100μA
S1 to S25: 1/3bias,I
O
= ±20μA
S1 to S25: 1/3bias, I
O
= ±20μA
COM1 to COM3: 1/3bias,I
O
= ±100μA
COM1 to COM3: 1/3bias,I
O
= ±100μA
OSC: R
OSC
= 39k
, C
OSC
= 1000pF
V
DD
:Sleep mode
V
DD
: V
DD
= 6.0V, output open,fosc = 38kHz
V
LCD
: Sleep mode
V
LCD
: V
LCD
= 6.0V, output open, 1/2bias,
fosc = 38kHz
V
LCD
– 1.0
V
LCD
– 1.0
V
LCD
– 1.0
V
LCD
– 1.0
V
LCD
– 0.5
V
LCD
– 0.2
Output high level voltage
V
0.2
0.5
1.5
1.0
Output low level voltage
1.0
V
1.0
0.1
0.5
1/2V
LCD
– 1.0
2/3V
LCD
– 1.0
1/3V
LCD
– 1.0
2/3V
LCD
– 1.0
1/3V
LCD
– 1.0
1/2V
LCD
+ 1.0
2/3V
LCD
+ 1.0
1/3V
LCD
+ 1.0
2/3V
LCD
+ 1.0
1/3V
LCD
+ 1.0
Output middle level voltage
*
2
V
Oscillator frequency
30.4
38
45.6
kHz
I
DD
1
I
DD
2
I
LCD
1
100
270
540
Current drain
5
μA
I
LCD
2
100
200
I
LCD
3
V
LCD
: V
LCD
= 6.0V, output open, 1/3bias,
fosc = 38kHz
60
120
Electrical Characteristics for the Allowable Operating Ranges
Note:
*
2. Excluding the bias voltage generation divider resistor built into V
LCD
1 and V
LCD
2. (See Figure 1.)
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Recommended external resistance
R
OSC
C
OSC
f
OSC
t
ds
t
dh
t
cp
t
cs
t
ch
t
H
t
L
t
r
t
f
t
dc
t
dr
OSC
39
k
pF
Recommended external capacitance
OSC
1000
Guaranteed oscillator range
OSC
19
38
76
kHz
Data setup time
CL, DI
:Figure 2
160
ns
Data hold time
CL, DI
:Figure 2
160
ns
CE wait time
CE, CL
:Figure 2
160
ns
CE setup time
CE, CL
:Figure 2
160
ns
CE hold time
CE, CL
:Figure 2
160
ns
High level clock pulse width
CL
:Figure 2
160
ns
Low level clock pulse width
CL
:Figure 2
160
ns
Rise time
CE, CL, DI
:Figure 2
160
ns
Fall time
CE, CL, DI
DO R
PU
=4.7k
, C
L
=10pF
*
1
DO R
PU
=4.7k
, C
L
=10pF
*
1
:Figure 2
160
ns
DO output delay time
:Figure 2
1.5
μs
DO rise time
:Figure 2
1.5
μs
Note:
*
1. Since DO is an open-drain output, these times depend on the values of the pull-up resistor R
PU
and the load capacitance C
L
.
Continued from preceding page.