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參數(shù)資料
| 型號： | LC74725 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Screen Display Controller LSI |
| 中文描述： | 屏幕顯示控制器芯片 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 260K |
| 代理商： | LC74725 |
No. 5213-4/16
LC74725, 74725M
Continued from preceding page.
Timing Characteristics
at Ta = –30 to +70°C, V
DD
1 = 5 V ± 0.5 V
Note: Follows the OSD timing for the CMOS output circuit type.
Figure 1 OSD Serial Data Input Timing
Parameter
Symbol
Conditions
min
typ
max
Unit
Border level 0
V
BK0
When the sync level is 0.8 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 1.0 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 0.8 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 1.0 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 0.8 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 1.0 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
1.43
1.55
1.67
V
1.61
1.73
1.85
V
Border level 1
V
BK1
2.01
2.13
2.25
V
2.18
2.30
2.42
V
Character level
V
CHA
2.57
2.69
2.81
V
2.76
2.88
3.00
V
Parameter
Symbol
Conditions
min
typ
max
Unit
OSD write (See Figure 1.)
Minimum input pulse width
t
W (SCLK)
t
W (CS1)
t
SU (CS1)
t
SU (SIN)
t
h (CS1)
t
h (SIN)
t
word
t
wt
SCLK
200
ns
CS1 (the period when CS1 is high)
1
μs
Data setup time
CS1
200
ns
SIN
200
ns
Data hold time
CS1
2
μs
SIN
200
ns
One-word write time
The time to write 8 bits of data
4.2
μs
The RAM data write time
1
μs
ESD read (See Figure 2 for the n-channel open-drain circuit.)
t
CKCY
t
CKL
t
CKH
t
ICK
t
CKO
SCLK
2
ns
Minimum input pulse width
SCLK
1
μs
SCLK
1
μs
Data setup time
SCLK
10
μs
Output delay time
CPDT
0.5
μs
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