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參數(shù)資料
| 型號： | LC72723M |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | RDS Demodulation IC |
| 中文描述： | 鐵路發(fā)展策略解調(diào)集成電路 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 114K |
| 代理商： | LC72723M |
RDCL/RDDA Output Timing
Master mode
No. 6037-6/8
LC72723, LC72723M
RST Operation
Master mode
RDCL Control in Slave Mode
Caution: After an RST input, the
RDCL and RDDA outputs
stop at the high level until
the first RDS ID detection.
Notes:1. Start RDCL clock input after the READY signal goes low. Applications must stand by with RDCL held low when the READY pin is high.
2. Each time the RDCL input is switched from low to high to low, the application must check the READY signal level after the period t
RC
has elapsed
once RDCL has been set low. If READY is at the low level, the application may apply the next RDCL clock cycle. If READY is high, the application
must stop RDCL input at that point.
3. When the above timing conditions are met, RDDA can be read at either the rise or fall of the RDCL signal.
4. After the last data from memory has been read, READY will be high once the period t
RC
has elapsed after the fall of the RDCL signal. If even 1 bit
of data has been written to memory, READY will be low and the application will be able to read that data.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
RDCL setup time
t
CS
t
CH
t
CL
t
DC
t
RC
t
RL
RDCL, RDDA
0
μs
RDCL high-level time
RDCL
0.75
μs
RDCL low-level time
RDCL
0.75
μs
Data output time
RDCL, RDDA
0.75
μs
READY output time
RDCL, READY
0.75
μs
Ready low-level time
READY
107
ms
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