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參數(shù)資料
| 型號： | LC72723M |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | RDS Demodulation IC |
| 中文描述： | 鐵路發(fā)展策略解調(diào)集成電路 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 114K |
| 代理商： | LC72723M |
No. 6037-4/8
LC72723, LC72723M
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
IN
1 max
V
IN
2 max
V
IN
3 max
Vo1 max
Vddd, Vdda
*
–0.3 to 7.0
V
TEST, MODE, RST
–0.3 to +7.0
V
Maximum input voltage
XIN, RDCL
–0.3 to Vddd + 0.3
V
MPXIN, CIN
–0.3 to Vdda + 0.3
V
RDS-ID (READY)
–0.3 to +7.0
V
Maximum output voltage
Vo2 max
XOUT, RDDA, RDCL
–0.3 to Vddd + 0.3
V
Vo3 max
FLOUT
–0.3 to Vdda + 0.3
V
Maximum output current
Io1 max
XOUT, FLOUT, RDDA, RDCL
+3.0
mA
Io2 max
RDS–ID (READY)
+20.0
mA
Allowable power dissipation
Pd max
(Ta
≤
85°C)
DIP16 : 300
mW
MFP16 : 140
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Specifications
Absolute Maximum Ratings
at Ta = 25°C, Vssd = Vssa = 0 V
*
: Note that Vdda must be less than or equal to Vddd + 0.3 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
V
IH
1
V
IH
2
V
IL
Vo1
Vddd, Vdda: Vddd = Vdda
4.5
5.0
5.5
V
High-level input voltage
TEST, MODE, RST
07 Vddd
6.5
V
RDCL
0.7 Vddd
Vddd
V
Low-level input voltage
TEST, MODE, RST, RDCL
0
0.3 Vddd
V
Output voltage
RDDA, RDCL
Vddd
V
Vo2
RDS–ID (READY)
6.5
V
V
IN
1
V
IN
2
VX
IN
Xtal
MPXIN
f = 57 ±2 KHz
50
mVrms
Input amplitude
100% modulation, composite
100
mVrms
XIN
XIN, XOUT: C1
≤
120
XIN, XOUT: Fo = 4.332 MHz
400
1500
mVrms
Guaranteed oscillator operating range
4.332
MHz
Crystal oscillator frequency deviation
TXtal
±100
ppm
RDCL setup time
t
CS
t
CH
t
CL
t
DC
t
RC
t
RL
RDCL, RDDA
0
μs
RDCL high-level time
RDCL
0.75
μs
RDCL low-level time
RDCL
0.75
μs
Data output time
RDCL, RDDA
0.75
μS
READY output time
RDCL, READY
0.75
μs
READY low-level time
READY
107
ms
Allowable Operating Ranges
at Ta = –40 to +85°C, Vssd = Vssa = 0 V, Vddd = Vdda
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