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參數(shù)資料
| 型號(hào)： | LC72714W |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder |
| 中文描述： | 多重移動(dòng)調(diào)頻廣播集成電路片VICS解碼器 |
| 文件頁數(shù)： | 13/29頁 |
| 文件大?。?/td> | 232K |
| 代理商： | LC72714W |
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No. 6871-13/29
LC72714W
Post-Correction Data Read Timing (DMA)
t
WRDM
t
DREQ
A0 to A3
DACK
DREQ
CS
t
CYDM
t
RDH
RD
DATn
*
:
*
:
*
:
A0 to A3: When post-correction data is read, A0 to A3 will be held fixed at 0.
DREQ and DACK: The polarity of these signals can be set.
Applications can select whether the DR or DACK signal is used for readout.
Layer 4 CRC Detection Circuit <Parallel Interface>
This function provides data group error detection, i.e. layer 4 CRC. When the stipulated number of bytes of data group
data and the CRC detection word (16 bits) are written to the layer 4 CRC register (address 6), if either the CRC4 pin
outputs a high level or the CRC4 flag (bit 1 in the status register at address 1) is set to 1 then there were no errors in the
data. The CRC4 pin or CRC4 flag in the status register outputs a high level if the IC internal CRC detection register bits
are all in the logic 0 state.
When this function is used to perform a layer 4 CRC check, applications must initialize the IC internal CRC detection
register before transferring the data for a single data group. This initialization is performed by sending data for bit 7
(CRC4_RST) in control register 1. Note that since this initialization flag is not automatically reset to 0, after the
application sets this flag it must then send another data item that resets it to 0 before sending the layer 4 CRC check data.
If there were no errors in all the received data groups, the CRC register will, necessarily, be all zeros after the CRC check
for a given data group. Therefore, as long as there are no errors detected in the layer 4 CRC check, the application does
not need to initialize the CRC detection register again using the control register as described above. There is no upper
limit on the total data length of data groups that can be transferred. Also, when the serial interface issued, the CCB
transfers can be divided into multiple transfer operations. The generating polynomial G(x) for the CRC code is as
follows. G(x) = X
16
+ X
12
+ X
5
+ 1
Structure of the Post-Correction Output Data <Parallel Interface>
The total length of the prepared output data is always 176 bits, i.e. 22 bytes. The layer 2 CRC data (14 bits) and the parity
data (82 bits) are not output. The data in each packet in the post-correction data is output in order starting at the
beginning in 8- or 16-bit units. BIC codes are not output.
When the CPU reads out the data, it can easily select the data by checking the status register first. The CPU can then
simply ignore data determined to be unnecessary without having to read it out by simply waiting until the next interrupt
arrives.
Structure of a Single Data Packet (Total length: 272 bits. BIC is not included.)
Data block (176 bits) Post-error correction data
*
: This data is not output.
Layer 2 CRC (14 bits)
Parity (82 bits)
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