參數(shù)資料
型號(hào)： LC72714W
廠商： Sanyo Electric Co.,Ltd.
英文描述： Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder
中文描述： 多重移動(dòng)調(diào)頻廣播集成電路片VICS解碼器
文件頁(yè)數(shù)： 11/29頁(yè)
文件大?。?/td> 232K
代理商： LC72714W
No. 6871-11/29
LC72714W
Data Update Timing for Read Registers
The data in the two read registers (the status register at address 01H and the block number register at address 02H) is
updated in the 1 ms interval between 1 ms prior to the output of the interrupt control signal (INT) and a point
immediately before the INT output.
In normal processing, when an interrupt occurs, the application will first determine the nature of the data packet that will
be output by the current interrupt signal by reading out the status register, and determine if it is necessary to read out that
data. For example, if error correction failed and the erroneous data is not required, the application should simply wait for
the next interrupt.
If the CCB interface is used, the application reads out the data from CCB address #FB, and determines the status from the
additional 16 bits of data. It then either reads out the following data or sets the CE signal low to cancel the readout.
Applications can also read out data asynchronously with respect to the interrupt signal. In this case, the application
checks the current reception status by reading out the status register and checking bit 6 (data received in the block
synchronized state) and bit 5 (data received in the frame synchronized state). In this case, using data for which bit 7 (VH)
is 0 provides superior real time characteristics.
CPU Interface Timing <Parallel Mode>
Register Read Timing
t
CYRD
t
WRDL1
, t
WRDL2
A0 to A3
CS
t
HARD
t
SARD
t
DRDY
t
RDH
t
WRDY
Valid
output
RD
RDY
DATn
*
t
HARD
stipulates the earliest timing for A0 to A3 and CS.
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參數(shù)描述
LC72715PW 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:CMOS IC Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder
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LC72720M 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Single-Chip RDS Signal-Processing System LSI
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