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參數(shù)資料
| 型號： | LC72711LW |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Mobile FM Multiplex Broadcast (DARC) Receiver IC(移動FM多路廣播接收器芯片) |
| 中文描述： | 移動調(diào)頻多路廣播（DARC）接收器IC（移動調(diào)頻多路廣播接收器芯片） |
| 文件頁數(shù)： | 18/29頁 |
| 文件大小： | 155K |
| 代理商： | LC72711LW |
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No. 6167-18/29
LC72711W, 72711LW
Layer 4 CRC Detection Circuit <Parallel Interface>
This function provides data group error detection, i.e. layer 4 CRC. When the stipulated number of bytes of data group
data and the CRC detection word (16 bits) are written to the layer 4 CRC register (address 6), if either the CRC4 pin
outputs a high level or the CRC4 flag (bit 1 in the status register at address 1) is set to 1 then there were no errors in the
data. The CRC4 pin or CRC4 flag in the status register outputs a high level, if the IC internal CRC detection register bits
are all in the logic 0 state.
When this function is used to perform a layer 4 CRC check, applications must initialize the IC internal CRC detection
register before transferring the data for a single data group. This initialization is performed by sending data for bit 7
(CRC4_RST) in control register 1. Note that since this initialization flag is not automatically reset to 0, after the
application sets this flag it must then send another data item that resets it to 0 before sending the layer 4 CRC check data.
If there were no errors in all the received data groups, the CRC register will, necessarily, be all zeros after the CRC check
for a given data group. Therefore, as long as there are no errors detected in the layer 4 CRC check, the application does
not need to initialize the CRC detection register again using the control register as described above. There is no upper
limit on the total data length of data groups that can be transferred. Also, when the serial interface issued, the CCB
transfers can be divided into multiple transfer operations. The generating polynomial G(x) for the CRC code is as
follows. G(x) = X
16
+ X
12
+ X
5
+ 1
Structure of the Post-Correction Output Data <Parallel Interface>
The total length of the prepared output data is always 176 bits, i.e. 22 bytes. The layer 2 CRC data (14 bits) and the parity
data (82 bits) are not output. The data in each packet in the post-correction data is output in order starting at the
beginning in 8- or 16-bit units. BIC codes are not output.
When the CPU reads out the data, it can easily select the data by checking the status register first. The CPU can then
simply ignore data determined to be unnecessary without having to read it out by simply waiting until the next interrupt
arrives.
Structure of a Single Data Packet (Total length: 272 bits. BIC is not included.)
Data block (176 bits) Post-error correction data
*
: This data is not output.
CPU Interface <CCB Mode>
CCB Format
Data is input and output using the CCB (Computer Control Bus) format, which is Sanyo’s audio IC serial bus format.
This IC uses an 8-bit address CCB with the address shown below. The CCB address is sent while CE is low, and the
CCB I/O mode is determined when CE is set high.
Data Input (Register Write)
Data is stored in an IC internal register. The CCB address #FA and 16 bits of data (DI0 to DI15) are input to the DI pin.
The bits are assigned as follows. Although DI12 to DI15 are unused data, arbitrary values must be provided to complete a
full 16 bits of data.
See the “Control Register” section earlier in this document for details on the register contents and addresses.
Details on writing to the layer 4 CRC check register are described later in this document. (The CCB address #FC is used
for this function.)
I/O mode
CCB address
Item
B0
B1
B2
B3
A0
A1
A2
A3
Input
0
1
0
1
1
1
1
1
16-bit control data input
Output
1
1
0
1
1
1
1
1
Data corresponding to the number of clock (CL) cycles is output
Input
0
0
1
1
1
1
1
1
Data input mode for the layer 4 CRC detection circuit (8-bit units)
Output
1
0
1
1
1
1
1
1
Register output only
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DI9
DI10
DI11
DI12 to DI15
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT0
BIT1
BIT2
BIT3
Unused data
(LSB)
Input data (8 bits)
(MSB)
Register address
Layer 2 CRC (14 bits)
Parity (82 bits)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72711LW-E | 制造商:ON Semiconductor 功能描述:DARC DECODE-LSI - Trays |
| LC72711LWHS-E | 功能描述:射頻接收器 RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| LC72711W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Mobile FM Multiplex Broadcast DARC Receiver IC |
| LC72711W_12 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Mobile FM Multiplex Broadcast (DARC) Receiver IC |
| LC72713W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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