參數(shù)資料
型號(hào): LC72711LW
廠商: Sanyo Electric Co.,Ltd.
英文描述: Mobile FM Multiplex Broadcast (DARC) Receiver IC(移動(dòng)FM多路廣播接收器芯片)
中文描述: 移動(dòng)調(diào)頻多路廣播(DARC)接收器IC(移動(dòng)調(diào)頻多路廣播接收器芯片)
文件頁(yè)數(shù): 14/29頁(yè)
文件大?。?/td> 155K
代理商: LC72711LW
No. 6167-14/29
LC72711W, 72711LW
BLK_RST
0: (default)
1: Resets the block synchronization circuit only.
Sets the block synchronization status to unsynchronized and clears the block synchronization protection counter.
However, note that this has no effect on the frame synchronization functions. Also note that during a
synchronization block reset, the INT signal is not output and the DO pin outputs a high level (high-impedance).
This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag.
SUBBLK
0: Normal status. (default)
1: Set to 1 when a substation (for example a dGPS station during VICS reception) is temporarily received.
Valid
output
RD
RDY
timing 1
timing 2
RDY
DATn
RDY Signal Output Timing
This is the data group write register used for the layer 4 CRC check. It is used only when the parallel interface is used.
Applications should specify the dedicated CCB address when using the serial interface.
Layer 4 CRC Register
Address
Register
R/W
Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
06H
CRC4
W
00H
(LSB)
Status Register
Address
Register
R/W
Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
01H
STAT
R
VH
BLK
FRM
ERR
PRI
HEAD
CRC4
RTIB
VH
0: Indicates data for which only horizontal correction was performed.
1: Indicates data for which after horizontal correction, vertical and then second horizontal correction were performed as
well.
Packet data with an RTIB flag is output with VH set to 0.
BLK
0: Indicates data that was received with block synchronization unsynchronized.
1: Indicates data that was received with block synchronization synchronized.
FRM
0: Indicates data that was received with frame synchronization unsynchronized.
1: Indicates data that was received with frame synchronization synchronized.
ERR
0: Indicates data for which error correction completed and no errors were detected in the level 2 CRC check.
1: Indicates data for which error correction was not possible or for which errors were detected in the level 2 CRC
check.
PRI
0: Indicates data that was inferred to be data block data by the frame synchronization circuit.
1: Indicates data that was inferred to be parity block data by the frame synchronization circuit.
Packet data with an RTIB flag is output with PRI set to 0.
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