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參數(shù)資料
| 型號(hào)： | LC72700E |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Mobile FM Multiplex Broadcast Receiver LSI(移動(dòng)FM多路廣播接收器) |
| 中文描述： | 多重移動(dòng)調(diào)頻廣播接收機(jī)的LSI（移動(dòng)調(diào)頻多路廣播接收器） |
| 文件頁(yè)數(shù)： | 11/14頁(yè) |
| 文件大?。?/td> | 200K |
| 代理商： | LC72700E |
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Interface: Basic Control Items
To reduce internal memory requirements this LSI limits the data buffer (RAM) area to the minimum required. Since data
received by the LSI is written to the buffer with no gaps, post-correction data that should be read may be overwritten by
new data if there are any delays in data readout.
The output timings for vertically and horizontally corrected data for this LSI are stipulated as follows.
1. When the output data is ready, the LSI sets the DO pin low and drops the INT-R pin to low.
2. In data output, there are periods during which only horizontal data can be read out and periods during which
horizontal and vertical data can be read out time-division multiplexed.
3. The data transfer must be completed within 9 ms after the DO pin goes low. When only horizontal data is output,
data can be transferred during a period of about 18 ms.
Even if the controlling CPU is still reading out data, the data in the output buffer can be overwritten by the next data
after the stipulated period has elapsed.
4. The amount of data that can be read in a single transfer request (INT-R) for both vertical and horizontal data is
limited to only one block of data.
In principle, vertical data is read out in order starting with block number 1 after vertical correction has completed.
Note that the parity block data is not output.
Figure 1 External Interface Basic Timing
Data Output Timing (as related to reception data)
Figure 2 shows the timing relationships between the reception data block start signal (BL-CK: pin 23) and the interrupt
control signal (INT-R: pin 25). However, this figure ignores the delay component with respect to the actual received
signal due to the demodulation operation in MSK demodulation blocks. Block synchronization is established by
recognizing BIC codes. As shown in Figure 2, the data from the nth packet (block) is available for output during
reception of the next packet, i.e. packet n+1. When using this LSI, be sure to keep in mind the fact that the block start
signal (BL-CK) output by the LSI is output after the BIC code in the actual reception data has been received.
Figure 3 shows the output timing for vertically corrected data. Vertical correction is used when a complete frame of data
is stored in memory, frame synchronization is established, and all the data packets could not be corrected by horizontal
correction. The frame start defines the timing for the start of vertical correction execution. Horizontal correction is
performed for each packet during reception of packets (blocks) 1 to 28 in the nth frame, and data is passed to the CPU
interface. Vertical correction is performed for the previous frame (frame n-1) data during the idle periods in the reception
process. (However, note that frame and block synchronization must not be lost.)
Vertically corrected data is output at the rate of one block for every block received in order starting with the 29th packet
(block). A total of 190 blocks of data are output. Of the data in the FM multiplex broadcast data structure, only the data
blocks are output, and the last block, the 190th block is output while the 218th block is being received.
No. 4870-11/14
LC72700E, LC72700G
INT-R
DO pin when only
horizontal data is output
DO pin when both
horizontal and vertical
data are output
Horizontal data output period
Horizontal data output period
Vertical data output period
(horizontal data)
(horizontal data)
Data not guaranteed
period
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| LC72706 | 制造商:SANYO 制造商全稱(chēng):Sanyo Semicon Device 功能描述:FM Multiplex Receiver IC Supporting All Worldwide Standards |
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