參數(shù)資料
型號： LC72321
廠商： Sanyo Electric Co.,Ltd.
英文描述： Single-Chip Microcontroller with PLL and LCD Driver
中文描述： 單片微控制器，帶有PLL和LCD驅(qū)動器
文件頁數(shù)： 13/13頁
文件大?。?/td> 234K
代理商： LC72321
No. 4796-13/13
LC72321
This catalog provides information as of December, 1997. Specifications and information herein are subject to
change without notice.
I
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
I
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
I
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Continued from preceding page.
Mnemonic
Operand
Function
Operation
Machine code
1st
2nd
D15 14 13 12 11 10 9 8
7 6 5 4
3 2 1 D0
LCD
M
I
Output segment pattern
to LCD digit direct
LCD (DIGIT)
←
M
1
1
1
0
0
0
DH
DL
DIGIT
LCP
M
I
Output segment pattern
to LCD digit through PLA
LCD (DIGIT)
←
PLA
←
M
1
1
1
0
0
1
DH
DL
DIGIT
IN
M
P
Input port data to M
M
←
(Port (P))
(Port (P))
←
M
(Port (P)) N
←
1
(Port (P)) N
←
0
if (Port (P)) N = all 1s,
then skip
1
1
1
0
1
0
DH
DL
P
OUT
M
P
Output contents of M to port
1
1
1
0
1
1
DH
DL
P
SPB
P
N
Set port bits
1
1
1
1
0
0
0 0
P
N
RPB
P
N
Reset port bits
1
1
1
1
0
1
0 1
P
N
Test port bits,
then skip if all bits
specified are true
TPT
P
N
1
1
1
1
1
0
1 0
P
N
Test port bits,
then skip if all bits
specified are false
if (Port (P)) N = all 0s,
then skip
TPF
P
N
1
1
1
1
1
1
1 1
P
N
UCS
I
Set I to UCCW1
UCCW1
←
I
0
0
0
0
0
0
0 1
0 0 0 0
I
UCC
I
Set I to UCCW2
UCCW2
←
I
0
0
0
0
0
0
1 1
0 0 0 0
I
FPC
N
F port I/O control
FPC latch
←
N
Stop clock if HOLD = 0
DAreg
←
DAC DATA
SIOCW
←
I1, I2
M
←
SIOreg
SIOreg
←
M
BEEPreg
←
I
0
0
0
1
0
0
0 0
0 0 0 0
N
CKSTP
Clock stop
0
0
0
1
0
0
0 1
0 0 0 0
0 0 0
0
DAC
I
Load M to D/A registers
0
0
0
0
0
0
1 0
0 0 0 0
I
SIO
I1
I2
Serial I/O control
0
0
0
1
0
0
1 1
I1
I2
SIOL
M
I
Load SIOreg to M
0
0
0
1
1
0
DH
DL
I
SIOS
M
I
Store M to SIOreg
0
0
0
1
0
1
DH
DL
I
BEEP
I
Beep control
0
0
0
1
0
0
1 0
0 0 0 0
I
NOP
No operation
0
0
0
0
0
0
0 0
0 0 0 0
0 0 0
0
I
g
I
U
i
O
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