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參數(shù)資料
| 型號： | LC7218M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 282K |
| 代理商： | LC7218M |
Sample Application System
TV/FM/AM (When IF count is performed)
Note: 1. The coupling capacitors used on the FMIN, AMIN, HCTR, and LCTR pins should be between 50 and 100 pF.
However, a 1000 pF capacitor should be used for LCTR if frequencies under 100 kHz are to be used.
2. Coupling capacitors should be located as close to their pin as possible.
3. When counting intermediate frequency signals, always have the controller first check for the presence of the
IF-IC SD signal and then only turn on the IF counter buffer output if the SD signal was present.
1. TV, 50 kHz steps
When the UHF RF = 637.75 MHz (IF = +10.7 MHz)
TV VCO = 648.45 MHz
PLL fref = 3.125 kHz
DV = 1, SP = * (FMIN selected)
Programmable divider divisor
Set N = 12969 (decimal).
2. FM, 100 kHz steps
When the FM RF = 90 MHz (IF = +10.7 MHz)
FM VCO = 100.7 MHz
PLL fref = 50 kHz
DV = 1, SP = * (FMIN selected)
Programmable divider divisor
Set N = 1007 (decimal).
3. AM, 10 kHz steps
When the AM RF = 1000 kHz (IF = +450 kHz)
AM VCO = 1450 kHz
PLL fref = 10 kHz
DV = 0, SP = 0 (AMIN, low speed measurement selected)
Programmable divider divisor
Set N = 145 (decimal).
*: Do not care
No. 4758-15/16
LC7218, 7218M, 7218JM
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