參數(shù)資料
型號: LC72148V
廠商: Sanyo Electric Co.,Ltd.
英文描述: Electronic Tuning PLL Frequency Synthesizer for Car Stereo Systems
中文描述: 電子調(diào)諧鎖相環(huán)頻率合成器的汽車音響系統(tǒng)
文件頁數(shù): 9/21頁
文件大?。?/td> 170K
代理商: LC72148V
No. 6974-9/21
LC72148V
DI control data functions
Number
Control block/data
Description
Related data
This data sets the divisor provided by the programmable divider. This is a binary value with
P15 the MSB. The LSB depends on the DVS and SNS settings. (
*
: don't care)
*
: When P4 is the LSB, P0 to P3 are ignored.
DVS selects the input pin (FMIN or AMIN) whose signal is input to the programmable divider
and SNS switches the input frequency range.
*
: See the “Structure of the Programmable Divider” item for details.
(1)
Programmable divider
data
P0 to P15
DVS, SNS
Sub-charge pump control data
*
: The sub-charge pump is connected to the gate of the low-pass filter amplifier transistor. A
high-speed locking circuit can be formed by using this function in conjunction with PD0 and
PD1 (main charge pump).
See the “Structure of the Charge Pump” item for details.
UL0
UL1
DLC
(2)
Sub-charge pump control
data
PDC0, PDC1
Reference frequency selection data
*
: PLL INHIBIT
In this state, the programmable divider is stopped, the FMIN and AMIN pins are pulled down to
ground, and the charge pump goes to the high-impedance state.
(3)
Reference divider data
R0 to R3
DVS
SNS
LSB
Set divisor (N)
1
*
P0
272 to 65535
0
1
P0
272 to 65535
0
0
P4
4 to 4095
R3
R2
R1
R0
Reference frequency
0
0
0
0
100 kHz
0
0
0
1
50
0
0
1
0
25
0
0
1
1
25
0
1
0
0
12.5
0
1
0
1
6.25
0
1
1
0
3.125
0
1
1
1
3.125
1
0
0
0
10
1
0
0
1
9
1
0
1
0
5
1
0
1
1
1
1
1
0
0
3
1
1
0
1
30
1
1
1
0
PLL inhibit + X’tal OSC stop
1
1
1
1
PLL inhibit
DVS
SNS
Input pin
Input pin frequency range
1
*
FMIN
10 to 180 MHz
0
1
AMIN
2 to 40 MHz
0
0
AMIN
0.5 to 10 MHz
PDC1
PDC0
Sub-charge pump state
0
*
High impedance
1
1
Charge pump operation (normal)
1
0
Charge pump operation (unlocked mode)
Continued on next page.
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