參數(shù)資料
型號(hào): LC72148V
廠商: Sanyo Electric Co.,Ltd.
英文描述: Electronic Tuning PLL Frequency Synthesizer for Car Stereo Systems
中文描述: 電子調(diào)諧鎖相環(huán)頻率合成器的汽車音響系統(tǒng)
文件頁(yè)數(shù): 5/21頁(yè)
文件大?。?/td> 170K
代理商: LC72148V
No. 6974-5/21
LC72148V
Pin Functions
Pin No.
Symbol
Type
Function
Pin circuit
Crystal resonator connections (7.2 or 4.5 MHz)
XIN
XOUT
24
1
X’tal
FMIN is selected when DVS in the serial data input is set to 1.
The input frequency range is 10 to 180 MHz.
The signal is directly transmitted to the swallow counter.
The divisor can be set to a value in the range 272 to 65,535.
FMIN
17
Local oscillator
signal input
AMIN is selected when DVS in the serial data input is set to 0.
When SNS in the serial data input is set to 1:
—The input frequency range is 2 to 40 MHz.
—The signal is directly transmitted to the swallow counter.
—The divisor can be set to a value in the range 272 to 65,535.
When SNS in the serial data input is set to 0:
—The input frequency range is 0.5 to 10 MHz.
—The signal is directly transmitted to the 12-bit programmable divider.
—The divisor can be set to a value in the range 5 to 4,095.
AMIN
16
Local oscillator
signal input
This pin must be set to the high level during serial data input (DI) from, or
serial data output (DO) to, the LC72148V.
CE
2
S
Chip enable
Input pin for serial data transmitted from the controller to the LC72148V.
DI
3
S
Input data
Data synchronization clock used during serial data input (DI) from, or
serial data output (DO) to, the LC72148V.
CL
4
S
Clock
Data output pin for data output from the LC72148V to the controller.
The content of the data output is determined by the ULD, DT0, and DT1
bits in the serial data.
DO
5
Output data
The LC72148V power supply pin. (V
DD
= 2.7 to 3.6 V)
The power-on reset circuit operates when power is first applied.
———
———
V
DD
15
Power supply
Digital system ground for the LC72148V
V
SSd
18
Ground
Connections to the internal n-channel MOS transistor provided to
implement an active low-pass filter for the PLL.
A high-speed locking circuit can be implemented by using these pins in
conjunction with the built-in sub-charge pump.
See the item describing the structure of the charge pump for details.
Vssa is a dedicated ground pin.
AIN
AOUT
V
SSa
21
22
23
Low-pass filter
amplifier transistor
Input/output shared-function pins
In output mode, the circuits are open-drain outputs.
The I/O direction is determined by I/O-1 to I/O-3 in the serial data.
When the data is 0: input port
When 1: output port
When specified for use as input ports
The input pin states are transmitted from the DO pin to the controller
Input state = low : Data = 0
Input state = high : Data = 1
When specified for use as output ports
The output states are determined by OUT1 to OUT3 in the serial data.
Data = 0 : low
Data = 1 : open
These pins are set to function as input ports by the power-on reset.
I/O-1
I/O-2
I/O-3
12
11
10
General-purpose
I/O ports
Continued on next page.
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