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參數(shù)資料
| 型號： | LC72146 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | PLL Frequency Synthesizer for Electronic Tuning(用于電子調(diào)諧的鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器電子調(diào)諧（用于電子調(diào)諧的鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 356K |
| 代理商： | LC72146 |
Continued from preceding page.
No. 4922-11/21
LC72146, 72146M
No.
Name
Function
Related bits
Input/output port control
Bits I/O1 to I/O5 set the direction of the ports. Each pin is an input when the corresponding bit is 0,
and an output, when the bit is 1. All ports are set to be inputs after power-on reset.
Output port data
Bits OUT1 to OUT7 set the output values of the O-1 to O-7 output ports. Each output is open or high when
the corresponding bit is 1, and low, when the bit is 0. A bit is ignored if the corresponding port is an input
port or the unlock output.
Counter input control
Bits H/I-6 and L/I-7 select the operation of the HCTR/I-6 and LCTR/I-7 pins. When H/I-6 is 0, HCTR/I-6 is an
input port, and when H/I-6 is 1, HCTR/I-6 is the HCTR input. When L/I-7 is 0, LCTR/I-7 is an input port, and
when L/I-7 is 1, LCTR/I-7 is the LCTR input.
PLL unlock detect control
Bits UL0 and UL1 select the phase error threshold and extension (E) used to detect the PLL unlocked
state as shown in Table 10 and Figure 4. When the phase error is greater than the selected error, the PLL
unlock detector output goes low.
Table 10 Unlock detection and extension selection
Figure 4 Phase-error extension
Crystal oscillator control
Bit XS selects the oscillator frequency. When XS is 1, the frequency is 7.2 MHz, and when XS is 0,
4.5 MHz.
4.5 MHz is selected after power-on reset.
Phase comparator control
Bits DZ0 and DZ1 select the phase comparator insensitive band, or dead zone.
Table 11 Insensitive band mode selection
DZA is selected after power-on reset.
Charge pump control
Bit DLC controls the charge pump operation. When DLC is 1, the charge pump outputs are forced to low,
and when DLC is 0, the charge pump operates normally.
This feature can be useful to remove the PLL from a deadlock state. The PLL can deadlock if its VCO
control voltage V
tune
becomes 0 V, halting the VCO. Setting DLC to 1 sets V
tune
to V
CC
, restarting the VCO.
Normal operating mode is selected after power-on reset.
An 8 Hz 40% duty clock time base signal can be output from pins 0 to 7 by setting TBC to 1.
When TBC is 1 the OUT7 data will be invalid. TBC is set to 0 by the power-on reset.
Test data
Bits TEST0 to TEST2 are used for in-factory device testing. Set them all to 0. They are set to zero after a
power-on reset.
(7)
(8)
I/O1 to I/O5
OUT1 to
OUT7
(9)
H/I6, L/I7
(10)
UL0, UL1
(11)
XS
(12)
DZ0, DZ1
(15)
TEST0 to
TEST2
(14)
TBC
(13)
DLC
OUT1 to OUT5, ULD
I/O1 to I/O5, ULD
CTS0, CTS1
ULD, DT0, DT1
OUT7
UL1
UL0
Phase error
Detector output
0
0
Stopped
Open
0
1
0
E output
1
0
±0.56 μs
E with 1 to 2 ms extension
1
1
±1.11 μs
E with 1 to 2 ms extension
DZ1
DZ0
Insensitive band (dead zone) mode
0
0
DZA
0
1
DZB
1
0
DZC
1
1
DZD
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72146M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
| LC72146MA-AH | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LC72146MHSQR-U-TRM-E | 制造商:Sony Semiconductor Solutions Division 功能描述: |
| LC72146V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC72147V | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems |
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