參數(shù)資料
型號(hào): LC72137M
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
封裝: MFP20
文件頁(yè)數(shù): 18/22頁(yè)
文件大?。?/td> 348K
代理商: LC72137M
No. 5743-5/22
LC72137, 72137M
Pin Descriptions
Pin No.
Symbol
(MFP pin numbers
Type
Functions
Circuit configuration
are in parentheses.)
20 (19)
21 (20)
13 (12)
12 (11)
2 (1)
4 (3)
3 (2)
5 (4)
15 (14)
16 (15)
XIN
XOUT
FMIN
AMIN
CE
CL
DI
DO
VDD
VSS
Xtal
Local oscillator
signal input
Local oscillator
signal input
Chip enable
Clock
Input data
Output data
Power supply
Ground
Crystal oscillator connections (75 kHz)
FMIN is selected when the serial data input DVS bit is
set to 1.
The input frequency range is from 10 to 160 MHz.
The input signal passes through the internal divide-by-
two prescaler and is input to the swallow counter.
The divisor can be in the range 272 to 65535. However,
since the signal has passed through the divide-by-two
prescaler, the actual divisor is twice the set value.
AMIN is selected when the serial data input DVS bit is
set to 0.
When the serial data input SNS bit is set to 1:
— The input frequency range is 2 to 40 MHz.
— The signal is directly input to the swallow counter.
— The divisor can be in the range 272 to 65535, and
the divisor used will be the value set.
When the serial data input SNS bit is set to 0:
— The input frequency range is 0.5 to 10 MHz.
— The signal is directly input to a 12-bit programmable
divider.
— The divisor can be in the range 4 to 4095, and the
divisor used will be the value set.
Set this pin high when inputting (DI) or outputting (DO)
serial data.
Used as the synchronization clock when inputting (DI) or
outputting (DO) serial data.
Inputs serial data transferred from the controller to the
LC72137.
Outputs serial data transferred from the LC72137 to the
controller. The data output is determined by the DOC0 to
DOC2 bits in the serial data.
The LC72137 power supply pin. (VDD = 2.5 to 3.6 V)
The power on reset circuit operates when power is first
applied.
The LC72137 ground
Continued on next page.
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