參數(shù)資料
型號: LC72137
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP22
封裝: SDIP-22
文件頁數(shù): 9/22頁
文件大小: 348K
代理商: LC72137
Unlock Detection Timing
1. Unlock Detection Determination Timing
Unlock detection is performed in the reference frequency (fref) period (interval). Therefore, in principle, unlock
determination requires a time longer than the period of the reference frequency. However, immediately after changing
the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the reference
frequency.
No. 5743-17/22
LC72137, 72137M
Figure 1 Unlock Detection Timing
For example, if fref is 1 kHz (and thus the period is 1 ms), after changing the divisor N, the system must wait at least
2 ms before checking for the unlocked state.
Figure 2 Circuit Structure
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