參數(shù)資料
型號(hào): LC72137
廠商: Sanyo Electric Co.,Ltd.
英文描述: PLL Frequency Synthesizer for Electronic Tuning(用于電子調(diào)諧的鎖相環(huán)頻率合成器)
中文描述: 鎖相環(huán)頻率合成器電子調(diào)諧(用于電子調(diào)諧的鎖相環(huán)頻率合成器)
文件頁(yè)數(shù): 11/22頁(yè)
文件大?。?/td> 348K
代理商: LC72137
No. 5743-11/22
LC72137, 72137M
Continued from preceding page.
DO Output Data (Serial Data Output) Structure
3. OUT mode
DO Output Data
No.
Control block/data
Description
Related data
IF counter control data
IFS
This data should be set to 1 in normal operation. Setting this data to 0 switches
the LC72137 to a reduced input sensitivity mode in which the sensitivity is reduced by
10 to 30 mVrms.
IC test data
TEST0
TEST1
All three bits must be set to 0.
TEST2
(11)
LSI test data
TEST 0 to TEST2
(12)
All the test data is set to 0 at a power-on reset.
(13)
DNC
Data is set to 0
No.
Control block/data
Description
Related data
I/O port data
I2, I1
Data latched from the states of the I/O ports, pins IO1 and IO2.
This data reflects the pin states, regardless of whether they are in input or output mode.
The data is latched when OUT mode is selected.
I1
IO1 pin state
High: 1
I2
IO2 pin state
Low: 0
Data latched from the state of the unlock detection circuit
UL
0: Unlocked
UL
1: Locked or in detection stopped mode
Data latched from the state of the IF counter, which is a 20-bit binary counter.
C19
Binary counter MSB
C0
Binary counter LSB
PLL unlock data
UL
IF counter binary data
C19 to C0
(1)
(2)
(3)
IOC1,
IOC2
UL0,
UL1
CTE,
GT0,
GT1
*
Note:
*
Data with a value of “0”
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