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參數(shù)資料
| 型號： | LC72137 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | PLL Frequency Synthesizer for Electronic Tuning(用于電子調(diào)諧的鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器電子調(diào)諧（用于電子調(diào)諧的鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 348K |
| 代理商： | LC72137 |
No. 5743-10/22
LC72137, 72137M
Continued from preceding page.
No.
Control block/data
Description
Related data
DO pin control data
DOC0, DOC1, DOC2
Data that determines DO pin output
The open state is selected following a power-on reset.
Note: 1. end-UC: IF counter measurement completion check
When end-UC is set and an IF count is started (CTE = 0
→
1), the DO pin
automatically goes to the open state.
When the IF count measurement completes, the DO pin goes low and
the count completion check operation is enabled.
The DO pin goes to the open state due to serial data I/O (CE: high).
2. Goes to the open state if the IO pin itself is set to be an output port.
Caution: The DO pin always goes to the open state during the data input period (during the
period when CE is high in mode IN1 or IN2), regardless of the values of the DO pin
control data (DOC0 to DOC2). Also, the DO pin outputs the content of the internal
DO serial data in synchronization with the CL pin signal during the data output period
(during the period when CE is high in the OUT mode) regardless of the values of
the DO pin control data (DOC0 to DOC2).
Unlock detection data
UL0, UL1
Selects the phase error (E) detection range for PLL lock discrimination.
When a phase error greater than the specified range occurs, the LC72137 determines
that the PLL is unlocked. (
*
: Don’t care.)
Note: When unlocked, the DO pin goes low and the serial data output UL bit is 0.
Phase comparator
control data
DZ0, DZ1
Phase comparator dead zone control data
Dead zone width: DZA < DZB < DZC < DZD
Clock time base
TBC
An 8 Hz 40% duty clock time base signal can be output from BO1 by setting TBC to 1.
(The BO1 data will be ignored.)
Charge pump control data
DLC
Data that forcibly controls the charge pump output
Note: The LC72137 provides a technique for escaping from deadlock by setting Vtune to
V
CC
(deadlock clear circuit). This is used when the circuit is deadlocked due to the
VCO oscillator being stopped by the VCO control voltage (Vtune) being 0 V.
(6)
(7)
(8)
(9)
(10)
UL0, UL1,
CTE,
IOC1, IOC2
DOC0,
DOC1,
DOC2
BO1
DOC2
DOC1
DOC0
DO pin state
0
0
0
0
0
0
1
1
0
1
0
1
Open
Low when the unlock state is detected
end-UC
*
1
Open
1
1
1
1
0
0
1
1
0
1
0
1
Open
The IO1 pin state
*
2
The IO2 pin state
*
2
Open
UL1
UL0
E detection width
Detector output
0
0
Stopped
Open
0
1
0
E is output directly
1
*
±6.67 μs
E is extended by 1 to 2 ms
DZ1
DZ0
Dead zone mode
0
0
DZA
0
1
DZB
1
0
DZC
1
1
DZD
DLC
Charge pump output
0
Normal operation
1
Forced low
Continued on next page.
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PDF描述 |
|---|---|
| LC72140 | PLL Frequency Synthesizer(鎖相環(huán)頻率合成器) |
| LC72144M | PLL Frequency Synthesizer(鎖相環(huán)頻率合成器) |
| LC72146 | PLL Frequency Synthesizer for Electronic Tuning(用于電子調(diào)諧的鎖相環(huán)頻率合成器) |
| LC72147V | PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72137_11 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer |
| LC72137M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
| LC72137MA-AE | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LC72140 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizers |
| LC72140M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizers |
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