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| 型號： | LC72135M |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | PLL Frequency Synthesizer for Electronic Tuning(用于電子調(diào)諧的鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器電子調(diào)諧（用于電子調(diào)諧的鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 300K |
| 代理商： | LC72135M |
Continued from preceding page.
3. DO Output Data (Serial Data Output)
OUT Mode
4. DO Output Data
No. 5175-13/24
LC72135M
No.
Control block/data
Functions
Related data
This data should be set to 1 during normal operation.
Note that if this value is set to zero the system enters input sensitivity degradation mode,
and the sensitivity is reduced to 10 to 30 mV rms.
*
See the “IF Counter Operation” item for details.
IF counter control data
IFS
(11)
LSI test data
TEST0
TEST1
TEST2
(12)
LSI test data
TEST 0 to 2
These values must all be set to 0.
These test data are set to 0 automatically after the power-on reset.
(13)
DNC
Don’t care. This data must be set to 0.
No.
Control block/data
Functions
Related data
I/O port data
I2, I1
Latched from the pin states of the LCTR/I1 input port (L/I1 bit is set to 0)
and the IO2 I/O port.
These values follow the pin states regardless of the input or output setting.
Data is latched when the data output mode is entered.
I1
←
LCTR/I1 pin state
High: 1
I2
←
IO2 pin state
Low: 0
Latched from the state of the unlock detection circuit.
UL
←
0: Unlocked
UL
←
1: Locked or detection stopped mode
Latched from the value of the IF counter (20-bit binary counter).
C19
←
MSB of the binary counter
C0
←
LSB of the binary counter
PLL unlock data
UL
IF counter binary data
C19 to C0
(1)
(2)
(3)
L/I1
IOC2
UL0,
UL1
CTE,
GT0,
GT1
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