tSPADDH Address Hold time after Clock Time — " />
參數(shù)資料
型號(hào): LC5512MV-45F484C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 36/99頁
文件大?。?/td> 0K
描述: IC XPLD 512MC 4.5NS 484FPBGA
標(biāo)準(zhǔn)包裝: 60
系列: ispXPLD® 5000MV
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 4.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 16
宏單元數(shù): 512
輸入/輸出數(shù): 253
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 484-BBGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
包裝: 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
37
tSPADDH
Address Hold time
after Clock Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tSPRWS
R/W Setup before
Clock Time
-0.27
-0.27
-0.27
-0.27
-0.21
ns
tSPRWH
R/W Hold time after
Clock Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tSPDATAS
Data Setup before
Clock Time
-0.27
-0.27
-0.27
-0.27
-0.21
ns
tSPDATAH
Data Hold time after
Clock Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tSPCLKO
Clock to Output
Delay
5.97
5.97
5.97
5.97
9.86
ns
tSPRSTO
Reset to RAM
Output Delay
3.30
3.30
3.30
3.30
4.29
ns
tSPRSTR
Reset Recovery
Time
1.20
1.20
1.20
1.20
1.56
ns
tSPRSTPW
Reset Pulse Width
0.14
0.14
0.14
0.14
0.19
ns
Pseudo Dual Port RAM
tPDPMSS
Memory Select
Setup Before Clock
-0.27
-0.27
-0.22
-0.22
-0.21
ns
tPDPMSH
Memory Select
Hold time after
Clock
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tPDPRCES
Clock Enable Setup
before Read Clock
Time
2.33
2.33
2.91
2.91
3.03
ns
tPDPRCEH
Clock Enable Hold
time after Read
Clock Time
-2.95
-2.95
-2.36
-2.36
-2.27
ns
tPDPWCES
Clock Enable Setup
before Write Clock
Time
1.87
1.87
2.34
2.34
2.43
ns
tPDPWCEH
Clock Enable Hold
time after Write
Clock Time
-2.95
-2.95
-2.36
-2.36
-2.27
ns
tPDPRADDS
Read Address
Setup before Read
Clock Time
-0.27
-0.27
-0.22
-0.22
-0.21
ns
tPDPRADDH
Read Address Hold
after Read Clock
Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tPDPWADDS
Write Address
Setup before Write
Clock Time
-0.27
-0.27
-0.22
-0.22
-0.21
ns
tPDPWADDH
Write Address Hold
after Write Clock
Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tPDPRWS
R/W Setup before
Clock Time
-0.27
-0.27
-0.22
-0.22
-0.21
ns
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
Base
Parameter
-4
-45
-5
-52
-75
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料
PDF描述
180-015-202L011 CONN DB15 FEMALE HD SLD CUP TIN
AMM15DTAH CONN EDGECARD 30POS R/A .156 SLD
AMM15DTAD CONN EDGECARD 30POS R/A .156 SLD
SG6742HRSY IC CTRLR PWM PROG GREEN CM 8SOP
TAJS225M010SNJ CAP TANT 2.2UF 10V 20% 1206
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC5512MV-45F484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-45F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-45F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-45FN208C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-45FN208I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family