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參數(shù)資料
| 型號(hào)： | LC4256V-5F256BC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| 中文描述： | EE PLD, 5 ns, PBGA256 |
| 封裝： | FPBGA-256 |
| 文件頁(yè)數(shù)： | 2/74頁(yè) |
| 文件大?。?/td> | 255K |
| 代理商： | LC4256V-5F256BC |
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
2
Table 2. ispMACH 4000Z Family Selection Guide
ispMACH 4000 Introduction
The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattice’s two most popular architectures: the ispLSI
2000 and ispMACH 4A. Retaining the best of both families,
the ispMACH 4000 architecture focuses on signi
fi
cant innovations to combine the highest performance with low
power in a
fl
exible CPLD family.
The ispMACH 4000 combines high speed and low power with the
fl
exibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-
binations in Thin Quad Flat Pack (TQFP) and Fine Pitch BGA (fpBGA) packages ranging from 44 to 256 pins/balls.
Table 1 shows the macrocell, package and I/O options, along with other key parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)
and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is con
fi
gured for 3.3V operation, making this family 5V tolerant. The ispMACH
4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up
resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/
2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary
scan testing capability also allows product testing on automated test equipment.
Overview
The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
contain multiple I/O cells. This architecture is shown in Figure 1.
ispMACH 4032ZC
32
32
3.5
2.2
3.0
267
1.8
20
48 TQFP
56 csBGA
1
ispMACH 4064ZC
64
32/64
4.0
2.8
3.3
250
1.8
25
48 TQFP
56 csBGA
100 TQFP
132 csBGA
2
ispMACH 4128ZC
128
64/96
4.5
2.9
3.9
220
1.8
30
2
ispMACH 4256ZC
256
64/96/128
5.0
3.0
3.9
200
1.8
40
Macrocells
User I/O Options
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
f
MAX
(MHz)
Supply Voltage (V)
Standby Icc (μA)
Pins/Package
100 TQFP
132csBGA
100 TQFP
132 csBGA
176 TQFP
1. Preliminary information.
2. Advance information.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC4256V-5F256BI | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4256V-5T144C | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4256V-5T144I | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4032ZC-35M56C | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
| LC4000B | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC4256V-5F256BC1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4256V-5F256BI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC4256V-5F256BI1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4256V-5FN256AC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC4256V-5FN256AC1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
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