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參數(shù)資料
| 型號： | LC4000Z |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
| 中文描述： | 3.3V/2.5V/1.8V在系統(tǒng)可編程超快高密度PDLs |
| 文件頁數(shù)： | 22/91頁 |
| 文件大?。?/td> | 851K |
| 代理商： | LC4000Z |
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
22
ispMACH 4000V/B/C External Switching Characteristics
Over Recommended Operating Conditions
Parameter
Description
1, 2, 3
-25
-27
-3
-35
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
t
PD
5-PT bypass combinatorial propagation
delay
—
2.5
—
2.7
—
3.0
—
3.5
ns
t
PD_MC
20-PT combinatorial propagation delay
through macrocell
—
3.2
—
3.5
—
3.8
—
4.2
ns
t
S
GLB register setup time before clock
1.8
—
1.8
—
2.0
—
2.0
—
ns
t
ST
GLB register setup time before clock
with T-type register
2.0
—
2.0
—
2.2
—
2.2
—
ns
t
SIR
GLB register setup time before clock,
input register path
0.7
—
1.0
—
1.0
—
1.0
—
ns
t
SIRZ
GLB register setup time before clock
with zero hold
1.7
—
2.0
—
2.0
—
2.0
—
ns
t
H
GLB register hold time after clock
0.0
—
0.0
—
0.0
—
0.0
—
ns
t
HT
GLB register hold time after clock with
T-type register
0.0
—
0.0
—
0.0
—
0.0
—
ns
t
HIR
GLB register hold time after clock, input
register path
0.9
—
1.0
—
1.0
—
1.0
—
ns
t
HIRZ
GLB register hold time after clock, input
register path with zero hold
0.0
—
0.0
—
0.0
—
0.0
—
ns
t
CO
t
R
t
RW
GLB register clock-to-output delay
—
2.2
—
2.7
—
2.7
—
2.7
ns
External reset pin to output delay
—
3.5
—
4.0
—
4.4
—
4.5
ns
External reset pulse duration
1.5
—
1.5
—
1.5
—
1.5
-
ns
t
PTOE/DIS
Input to output local product term output
enable/disable
—
4.0
—
4.5
—
5.0
—
5.5
ns
t
GPTOE/DIS
Input to output global product term
output enable/disable
—
5.0
—
6.5
—
8.0
—
8.0
ns
t
GOE/DIS
t
CW
Global OE input to output enable/disable
—
3.0
—
3.5
—
4.0
—
4.5
ns
Global clock width, high or low
1.1
—
1.3
—
1.3
—
1.3
—
ns
t
GW
Global gate width low (for low
transparent) or high (for high transparent)
1.1
—
1.3
—
1.3
—
1.3
—
ns
t
WIR
f
MAX
Input register clock width, high or low
1.1
—
1.3
—
1.3
—
1.3
—
ns
4
Clock frequency with internal feedback
400
—
333
—
322
—
322
—
MHz
f
MAX
(Ext.)
Clock frequency with external feedback,
[1/ (t
S
+ t
CO
)]
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
250
—
222
—
212
—
212
—
MHz
Timing v.3.2
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