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參數(shù)資料
| 型號： | LC4000C |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
| 中文描述： | 3.3V/2.5V/1.8V在系統(tǒng)可編程超快高密度PDLs |
| 文件頁數(shù)： | 7/91頁 |
| 文件大?。?/td> | 851K |
| 代理商： | LC4000C |
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
7
Table 5. Product Term Expansion Capability
Every time the super cluster allocator is used, there is an incremental delay of t
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
EXP
. When the super cluster alloca-
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Enhanced Clock Multiplexer
The clock input to the
fl
ip-
fl
op can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
Block CLK0
Block CLK1
Expansion
Chains
Macrocells Associated with Expansion Chain
(with Wrap Around)
Max PT/
Macrocell
Chain-0
M0
→
M4
→
M8
→
M12
→
M0
75
Chain-1
M1
→
M5
→
M9
→
M13
→
M1
80
Chain-2
M2
→
M6
→
M10
→
M14
→
M2
75
Chain-3
M3
→
M7
→
M11
→
M15
→
M3
70
Single PT
Block CLK0
Block CLK1
Block CLK2
Block CLK3
PT Clock (optional)
Shared PT Clock
CE
D/T/L
Q
R
P
Shared PT Initialization
PT Initialization/CE (optional)
PT Initialization (optional)
From Logic Allocator
Power-up
Initialization
To ORP
To GRP
From I/O Cell
Delay
相關(guān)PDF資料 |
PDF描述 |
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| LC4000V | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
| LC4000Z | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
| LC4512x | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
| LC4512Z | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
| LC4128ZC-42M132C1 | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC4000V | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
| LC4000Z | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
| LC4001B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| LC4001BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| LC401 | 制造商:POLYFET 制造商全稱:Polyfet RF Devices 功能描述:SILICON GATE ENHANCEMENT MODE RF POWER LDMOS TRANSISTOR |
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