參數(shù)資料
型號(hào)： LC4000B
廠商： Lattice Semiconductor Corporation
英文描述： 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
中文描述： 3.3V/2.5V/1.8V在系統(tǒng)可編程超快高密度PDLs
文件頁(yè)數(shù)： 8/91頁(yè)
文件大?。?/td> 851K
代理商： LC4000B
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
8
Block CLK2
Block CLK3
PT Clock
PT Clock Inverted
Shared PT Clock
Ground
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
PT Initialization/CE
PT Initialization/CE Inverted
Shared PT Clock
Logic High
Initialization Control
The ispMACH 4000 family architecture accommodates both block-level and macrocell-level set and reset capability.
There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macrocell
level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset func-
tionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing
fl
exibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All
fl
ip-
fl
ops power up to a
known state for predictable system initialization. If a macrocell is con
fi
gured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is con
fi
gured to RESET on a
signal from the block-level initialization or is not con
fi
gured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the V
CC
rise must be monotonic, and the clock must be inactive until the reset
delay time has elapsed.
GLB Clock Generator
Each ispMACH 4000 device has up to four clock pins that are also routed to the GRP to be used as inputs. These
pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock signals that
can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the
true and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
CLK0
CLK1
CLK2
CLK3
Block CLK0
Block CLK1
Block CLK2
Block CLK3
相關(guān)PDF資料
PDF描述
LC4000C 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
LC4000V 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
LC4000Z 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
LC4512x 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
LC4512Z 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC4000C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
LC4000V 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
LC4000Z 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
LC4001B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Logic IC
LC4001BM 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Logic IC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*