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| 型號： | LB1876(36SOP) |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 120K |
| 代理商： | LB1876(36SOP) |
No. 6201-3/14
LB1876
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
[Phase comparator output]
Output High level voltage
VPDH
I
O
H = –100 μA
I
O
H = 100 μA
VPD = VREG/2
VREG-0.2
VREG-0.1
V
Output Low level voltage
VPDL
0.2
0.3
V
Output source current
IPD+
–0.5
mA
Output sink current
IPD–
VPD = VREG/2
1.5
mA
[Phase lock detector output]
Output saturation voltage
V
O
L(LD)
IL(LD)
ILD = 10 mA
0.15
0.5
V
Output leak current
V
O
= V
CC
10
μA
[ERR amplifier]
Input offset voltage
V
I
O(ER)
I
B
(ER)
V
O
H(ER)
V
O
L(ER)
VB(ER)
Design target value
–10
+10
mV
Input bias current
–1
+1
μA
Ouput High level voltage
I
O
H = –500 μA
I
O
L = 500 μA
VREG–1.2
VREG-0.9
V
Ouput Low level voltage
0.9
1.2
V
DC bias level
–5%
VREG/2
+5%
V
[Current limiter]
Drive gain 1
GDF1
in phase lock mode
0.4
0.5
0.6
times
Drive gain 2
GDF2
in unlock mode
0.8
1.0
1.2
times
Limiter voltage
VRF
V
CC
- V
M
0.45
0.5
0.55
V
[Thermal shutdown operation]
Termal shutdown operating temperature
TSD
TSD
Design target value (junction temperature)
150
180
°C
Hysteresis width
Design target value (junction temperature)
40
°C
[Low voltage protection]
Operating voltage
VSD
VSD
8.1
8.5
8.9
V
Hysteresis
0.2
0.35
0.5
V
[CLD circuit]
External capacitor charge current
ICLD
–6
–4.3
–3
V
Operating voltage
VH(CLD)
3.25
3.5
3.75
V
[CLK pin]
External input frequency
fI(CKIN)
0.1
10
kHz
High level input voltage
V
I
H(CKIN)
V
I
L(CKIN)
V
I
O(CKIN)
V
I
S(CKIN)
I
I
H(CKIN)
I
I
L(CKIN)
3.5
VREG
V
Low level input voltage
0
1.5
V
Input open voltage
VREG-0.5
VREG
V
Hysteresis width
0.35
0.5
0.65
V
High level input current
VCKIN = VREG
–10
0
+10
μA
Low level input current
VCKIN = 0 V
–280
–210
μA
[S/S pin]
High level input voltage
V
I
H(SS)
V
I
L(SS)
V
I
O(SS)
V
I
S(SS)
I
I
H(SS)
I
I
L(SS)
3.5
VREG
V
Low level input voltage
0
1.5
V
Input open voltage
VREG-0.5
VREG
V
Hysteresis width
0.35
0.5
0.65
V
High level input current
VS/S = VREG
–10
0
+10
μA
Low level input current
VS/S = 0 V
–280
–210
μA
[LDSEL pin]
High level input voltage
V
I
H(LD
SEL
)
V
I
L(LD
SEL
)
V
I
O(LD
SEL
)
I
I
H(LD
SEL
)
I
I
L(LD
SEL
)
3.5
VREG
V
Low level input voltage
0
1.5
V
Input open voltage
VREG-0.5
VREG
V
High level input current
V
LDSEL
= VREG
V
LDSEL
= 0 V
–10
0
10
μA
Low level input current
–280
–210
μA
[BRSEL pin]
High level input voltage
V
I
H(BR
SEL
)
V
I
L(BR
SEL
)
V
I
O(BR
SEL
)
I
I
H(BR
SEL
)
V
LDSEL
= VREG
I
I
L(BR
SEL
)
V
LDSEL
= 0 V
3.5
VREG
V
Low level input voltage
0
1.5
V
Input open voltage
VREG-0.5
VREG
V
High level input current
–10
0
10
μA
Low level input current
–280
–210
μA
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