參數(shù)資料
型號： LAN91C100FD
廠商： SMSC Corporation
英文描述： FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
中文描述： 宴快速以太網控制器以全雙工能力
文件頁數(shù)： 59/79頁
文件大?。?/td> 585K
代理商： LAN91C100FD
FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC DS – LAN91C100FD Rev. D
Page 59
Rev.
10/14/2002
PRELIMINARY
7.3
High End ISA or Non-Burst EISA Machines
On ISA machines, the LAN91C100FD is accessed as a 16 bit peripheral. No support for XT (8 bit
peripheral) is provided. The signal connections are listed in the following table:
Table 7.2 - High-End ISA or Non-Burst EISA Machines Signal Connectors
ISA BUS
SIGNAL
A1-A15
AEN
nIORD
LAN91C100FD
SIGNAL
A1-A15
AEN
nRD
NOTES
Address bus used for I/O space and register decoding.
Qualifies valid I/O decoding - enabled access when low.
I/O Read strobe - asynchronous read accesses. Address is valid
before leading edge.
I/O Write strobe - asynchronous write access. Address is valid
before leading edge. Data is latched on trailing edge.
This signal is negated on leading nRD, nWR if necessary. It is
then asserted on CLK rising edge after the access condition is
satisfied.
16 bit data bus. The bus byte(s) used to access the device are a
function of nBE0 and nBE1:
nBE0
nBE1
D0-D7
0
0
Lower
0
1
Lower
1
0
Not used
Not used = tri-state on reads, ignored on writes
nLDEV is a totem pole output. Must be buffered using an open
collector driver. nLDEV is active on valid decodes of A15-A4 and
AEN=0.
UNUSED PINS
No upper word access.
nIOWR
nWR
IOCHRDY
ARDY
RESET
A0
nSBHE
IRQn
D0-D15
RESET
nBE0
nBE1
INTR0-INTR3
D0-D15
D8-D15
Upper
Not used
Upper
nIOCS16
nLDEV buffered
GND
VCC
LCLK nADS
nBE2 nBE3
nCYCLE W/nR
nRDYRTN
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