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參數(shù)資料
| 型號： | LAN91C100-FD |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY |
| 中文描述： | 2 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | QFP-208 |
| 文件頁數(shù)： | 62/79頁 |
| 文件大?。?/td> | 585K |
| 代理商： | LAN91C100-FD |
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FEAST Fast Ethernet Controller with Full Duplex Capability
Rev.
10/14/2002
Page 62
SMSC DS – LAN91C100FD Rev. D
PRELIMINARY
EISA BUS
SIGNAL
nEX32
nNOWS
(optional
additional logic)
LAN91C100FD
SIGNAL
nLDEV
NOTES
nLDEV is a totem pole output. nLDEV is active on valid
decodes of LAN91C100FD pins A15-A4, and AEN=0.
nNOWS is similar to nLDEV except that it should go inactive
on nSTART rising. nNOWS can be used to request
compressed cycles (1.5 BCLK long, nRD/nWR will be 1/2
BCLK wide).
THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES
BCLK
LCLK
EISA Bus Clock. Data transfer clock for DMA bursts.
nDAK<n>
nDATACS
DMA Acknowledge. Active during Slave DMA cycles. Used
by the LAN91C100FD as nDATACS direct access to data
path.
nIORC
W/nR
Indicates the direction and timing of the DMA cycles. High
during LAN91C100FD writes, low during LAN91C100FD
reads.
nIOWC
nEXRDY
nRDYRTN
EISA bus signal indicating whether a slave DMA cycle will
take place on the next BCLK rising edge, or should be
postponed. nRDYRTN is used as an input in the slave DMA
mode to bring in EXRDY.
UNUSED PINS
VCC
nVLBUS
GND
A1
nCYCLE
Indicates slave DMA writes.
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| LAN91C100FD(208PQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
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| LAN91C100FD_0601 | 制造商:SMSC 制造商全稱:SMSC 功能描述:FEAST Fast Ethernet Controller with Full Duplex Capability |
| LAN91C100FDQFP | 制造商:Rochester Electronics LLC 功能描述: 制造商:SMSC 功能描述: |
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