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參數資料
| 型號： | LA79500E |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | 6-CHANNEL, VIDEO MULTIPLEXER, QFP80 |
| 封裝： | 14 X 20 MM, QIP-80 |
| 文件頁數： | 5/16頁 |
| 文件大?。?/td> | 653K |
| 代理商： | LA79500E |
LA79500E
No.A0259-13/16
3) Initialize
SW LSI is initialized as the following mode for circuit protection. Please see “SERIAL CONTROL TABLE”.
Characteristics of the SDA and SCL 1/0 stages for SW LSI
Ratings
Parameter
Symbol
Min
Max
Unit
LOW level input voltage
VIL
0
1.5
V
HIGH level input voltage
VIH
3.5
5.0
V
LOW level output current
IOL
3.0
mA
SCL clock frequency
fSCL
100
kHz
Set-up time for a repeated START condition
tSU:STA
4.7
s
Hold time START condition. After this period, the first clock pulse is generated.
tHD:STA
4.0
s
LOW period of the SCL clock
tLOW
4.7
s
Rise time of both SDA and SDL signals
tR
0
1.0
s
HIGH period of the SCL clock
tHIGH
4.0
s
Fall time of both SDA and SDL signals
tF
0
1.0
s
Data hold time
tHD:DAT
0
s
Data set-up time
tSU:DAT
250
ns
Set-up time for STOP condition
tSU:STO
4.0
s
BUS fred time between a STOP and START condition
tBUF
4.7
s
Fig.2 Definition of timing
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|---|---|
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