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LA79500E
No.A0259-12/16
1) Data transfer manual : [1] is High level. [0] is Low level.
I
2C-BUS control system is adopted in SW LSI and SW LSI is controlled by SCL (Serial Clock) and SDA (Serial
Data). At first, please set up the START condition*1 by these two terminals (SCL and SDA). And next, please input
the 8bits data which should be synchronized with SCL into SDA terminal Still more, please give priority to high
rank bit at data transfer order (MSB
→LSB). The 9th bit is called as ACK (Acknowledge), SW LSI sends [0] to the
SDA terminal during SCL [1] period. So, please open the port of micro-processor during this period. And next,
please transfer sub-address data (called as Group) and control data. As thus the Data transfer Stop condition*2 is
finished.
*1 : SDA rise up during SCI is [1]
*2 : SDA fall down during SCL is [1]
2) Transfer data format
The transfer data is composed by START condition , Slave address data, sub-address data, control data and STOP
condition.
There are 6 control groups.
After setting up the START condition, please transfer the Slave Address. sub-address data and next control data
(Please see the Fig.1)
Slave Address is composed by 7bits, and this bit 8th bit should be set as [0] at write mode and [1] at read mode.
This 8th bit called as R/W bit, and this bit shows the data transmission direction. [0] means send mode (accept mode
with SW LSI) and [1] means accept mode (send mode with SW LSI) fundamentally.
The both of sub-address data and control data are composed by 8bits, and the one control action is defined with
combination of these two data. And if you want to control 2 or more groups at the same mode, you can realize it by
sending some control data together.
The data makes meaning with all bits, so you cannot stop the sending until all data transfer is over. If you want to
stop transfer action, please transfer the STOP condition.
You can select how to send as follws.(write mode)
Pattern A Start condition + Slave Address + Sub Address 00 + Data 00 + Data 01 + Data 02 + Data 03 +
Data 04 + Data 05 + Stop condition
Pattern B Start condition + Slave Address + Sub Address 01 + Data 01 + Data 02 + Data 03 + Data 04 +
Data 05 + Stop condition
Pattern C Start condition + Slave Address + Sub Address 02 + Data 02 + Data 03 + Data 04 + Data 05 +
Stop condition
Pattern D Start condition + Slave Address + Sub Address 03 + Data 03 + Data 04 + Data 05 + Stop condition
Pattern E Start condition + Slave Address + Sub Address 04 + Data 04 + Data 05 + Stop condition
Pattern F Start condition + Slave Address + Sub Address (01 or 02 or 03 or 04 or 05) +
Data (01 or 02 or 03 or 04 or 05) + Stop condition (send only 1Data)
START condition
Slave Address
R/W
ACK
Sub-Address
ACK
Control data
ACK
...
STOP condition
Fig.1 Data Structure