參數(shù)資料
型號(hào)： L8708H
廠商： ZiLOG, Inc.
英文描述： IR/Low-Voltage Microcontroller
中文描述： 紅外/低電壓微控制器
文件頁數(shù)： 53/66頁
文件大?。?/td> 599K
代理商： L8708H
Z86L88/81/86/87/89/73
IR/Low-Voltage Microcontroller
DS96LV00800
P R E L I M I N A R Y
53
1
WDT Time Select
(D0, D1). Selects the WDT time period.
It is configured as shown in Table 8.
WDTMR During HALT
(D2). This bit determines whether
or not the WDT is active during HALT mode. A 1 indicates
active during HALT. The default is 1.
WDTMR During STOP
(D3). This bit determines whether
or not the WDT is active during STOP mode. Since the
XTAL clock is stopped during STOP mode, the on-board
RC has to be selected as the clock source to the
WDT/POR counter. A 1 indicates active during STOP. The
default is 1.
Clock Source for WDT
(D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configu-
ration of this bit is 0, which selects the RC oscillator.
Table 8. WDT Time Select
D1
0
0
1
1
D0
0
1
0
1
Time-Out of
Internal RC OSC
5 ms min
10 ms min
20 ms min
80 ms min
Time-Out of
XTAL Clock
256 TpC
512 TpC
1024 TpC
4096 TpC
Notes:
TpC = XTAL clock cycle.
The default on reset is 10 ms.
Figure 44. Resets and WDT
CLK
18 Clock RESET
Generator
RESET
* /CLR 2
WDT TAP SELECT
INTERNAL
RC
OSC.
CLK
*CLR1
POR
WDT1
2
3
4
Low Operating
Voltage Det.
Internal
RESET
Active
High
CK Source
Select
(WDTMR)
XTAL
VDD
VBO/VLV
2V REF
From Stop
Mode
Recovery
Source
WDT
Stop Delay
Select (SMR)
12 ns Glitch Filter
+
-
5 Clock
Filter
WDT/POR Counter Chain
M
U
X
/RESET
* /CLR1 and /CLR2 enable the WDT/POR and
18 Clock Reset timers upon a Low to High input translation.
VCC
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