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參數(shù)資料
| 型號： | L7250 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 5V & 12V SPINDLE AND VCM MOTORS DRIVER |
| 中文描述： | 5V的 |
| 文件頁數(shù)： | 21/46頁 |
| 文件大小： | 478K |
| 代理商： | L7250 |
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L7250
2
SPINDLE MOTOR CONTROLLER
Figure 3.
2.1 Spindle Smoothdrive Functionality
L7250 utilizes ST's proprietary Smoothdrive commutation algorithm. Smoothdrive is a voltage mode pseudo-
sinusoidal spindle drive scheme where the duty cycles of the three windings are modulated to form sinusoidal
voltages across each winding. The system determines the shape and amplitude of the driving voltages in a
completely digital manner.
2.2 SYSCLK
The Smoothdrive system clock comes through the SYSCLK pin.
The system expects either 33MHz or 16.5MHz on this pin, and needs 16.5MHz internally. A SYSCLK divide by
two can be enabled by a SPI register bit PRESMO to accomodate a 33MHz external clock.
2.3 Smoothdrive Wave shape
The basic Smooth drive wave shape is stored in digital memory. A voltage profile designed to reduce switching
losses and increase the voltage headroom has been implemented. Essentially, two phases are PWM'ed, while
the low side driver of the third phase is on at 100% duty cycle. The PWM duty cycles are modulated in such a
way as to result in sinusoidal currents on all 3 motor phases. Driving in this manner, as opposed to driving true
sinusoids on all three phases, results in improved headroom and efficiency, approaching that of conventional 6
state commutation.
The system is phase locked to the motor by sensing one BEMF zero crossing on one winding, once per electrical
VM
HGU
MOTU
LGU
FET
GATE
DRIVE
VM
HGV
MOTV
LGV
FET
GATE
DRIVE
VM
HGW
MOTW
LGW
FET
GATE
DRIVE
xx
SMOOTHDRIVE
LOGIC
(N=48)
MDIGITAL
CO&
COMPARATORS
xx
CTAP
WINDOW
MASK
PWM MASK
CZERO
PERIOD
16+4 BIT
CFSCAN
ZC
Tc
FSCAN
BEMF
COMP.
CURRENT
LIMIT
COMP.
ADVANCE
BIT
OLSIX/OLSIN
KVAL
REGISTER
KVAL
PHASE
ABITS
ABITS
SYSCLK
16.5MHZ
SPINDLE
MOTOR
LBIT
SMOOTHDRIVE
DURAW
MODULATED
DUTY CYCLE
DUTY CYCLE
SIGNALS
SPSENH
VM
ADC
START-OF-COUNT
SUPPLY
COVOLTAGE
MASK
REGISTERS
WINDOW
TRISTATE
CMD
6 or
Sine
CUR DAC
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