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參數(shù)資料
| 型號(hào)： | L6732TR |
| 廠(chǎng)商： | 意法半導(dǎo)體 |
| 英文描述： | Adjustable step-down controller with synchronous rectification |
| 中文描述： | 可調(diào)式降壓同步整流控制器 |
| 文件頁(yè)數(shù)： | 7/33頁(yè) |
| 文件大?。?/td> | 735K |
| 代理商： | L6732TR |
L6732
Pin connections and functions
7/33
3
Pin connections and functions
Figure 2.
Pins connection ( Top view)
Table 3.
Pin functions
Pin n.
Name
Function
1
PGOOD
This pin is an open collector output and it is pulled low if the output voltage is not
within the specified thresholds (90%-110%). If not used it may be left floating. Pull-up
this pin to V
CCDR
with a 10K resistor to obtain a logical signal.
2
SYNCH
It is a Master-Slave pin. Two or more devices can be synchronized by simply
connecting the SYNCH pins together. The device operating with the highest FSW will
be the Master. The Slave devices will operate with 180° phase shift from the Master.
The best way to synchronize devices together is to set their FSW at the same value. If
it is not used the SYNCH pin can be left floating.
3
SGND
All the internal references are referred to this pin.
4
FB
This pin is connected to the error amplifier inverting input. Connect it to V
OUT
through
the compensation network. This pin is also used to sense the output voltage in order
to manage the over voltage conditions and the PGood signal.
5
COMP
This pin is connected to the error amplifier output and is used to compensate the
voltage control feedback loop.
6
SS/INH
The soft-start time is programmed connecting an external capacitor from this pin and
GND. The internal current generator forces a current of 10 A through the capacitor.
When the voltage at this pin is lower than 0.5V the device is disabled.
1
2
3
4
5
6
11
12
HTSSOP16
13
14
15
16
SGND
EAREF
OCL
FB
PGOOD
SYNCH
COMP
SS/INH
VCC
LGATE
PHASE
OCH
PGND
7
10
VCCDR
BOOT
HGATE
8
9
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