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參數(shù)資料
| 型號： | L6731BTR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Transistor; Type: Amplifiers/Bipolar; VCEO (V): -25; Ic (A): -1; Pc (W): 0.8; hFE: 85 to 330; VCE (sat) (V) max: -0.5; Package: TO-92Mod |
| 中文描述： | 可調(diào)式降壓同步整流專用的DDR控制器內(nèi)存 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 311K |
| 代理商： | L6731BTR |
Application details
L6731B
20/24
The compensation network consists in the internal error amplifier, the impedance networks Z
IN
(R3, R4 and C20) and Z
FB
(R5, C18 and C19). The compensation network has to provide a
closed loop transfer function with the highest 0dB crossing frequency to have fastest transient
response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the
load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade
slope and a phase margin greater than 45°. To locate poles and zeroes of the compensation
networks, the following suggestions may be used:
Modulator singularity frequencies:
●
●
Compensation network singularity frequencies:
●
Compensation network design:
–
Put the gain R
5
/R
3
in order to obtain the desired converter bandwidth
–
Place
ω
Z1
before the output filter resonance
ω
LC
;
Place
ω
Z2
at the output filter resonance
ω
LC
;
Place
ω
P1
at the output capacitor ESR zero
ω
ESR
;
Place
ω
P2
at one half of the switching frequency;
Check the loop gain considering the error amplifier open loop gain.
–
–
–
–
Figure 12. Asymptotic Bode plot of Converter's open loop gain
Cout
L
LC
=
1
ω
Cout
ESR
ESR
=
1
ω
(13)
(14)
+
=
19
18
19
18
5
1
1
C
C
C
C
R
P
ω
20
4
2
1
C
R
P
=
ω
(15)
(16)
19
5
1
1
C
R
Z
=
ω
(
)
4
3
20
2
1
R
R
C
Z
+
=
ω
(17)
(18)
LC
C
Vosc
Vin
R
R
=
3
5
(19)
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