參數(shù)資料
型號: L6585DETR
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: POWER FACTOR CONTROLLER, PDSO20
封裝: ROHS COMPLIANT, SOP-20
文件頁數(shù): 19/33頁
文件大小: 2064K
代理商: L6585DETR
Ballast section
L6585DE
26/33
Figure 15.
Example of capacitive mode operation due to ballast choke saturation
Therefore, in ignition and run mode a comparator, connected to the HBCS pin, is active with
a threshold respectively equal to 2.75 V and 1.6 V. It senses very high currents flowing in the
ballast sense resistor and immediately latches the IC in low consumption mode. The width
of the triggering spike is above 200 ns. This guarantees that, during run mode, hard
switching events (typical duration between 40 ns and 100 ns) cannot trigger the comparator.
However, hard switching protection and anti-saturation protection are not perfectly
independent. Regarding the pulse width we can indicate four different regions:
a)
Spikes with a duration less than 40 ns: (noise region) no protection can be
triggered.
b)
Spikes with a duration between 40 ns and 100 ns: (HSw region) only hard
switching protection will be activated after around 420 events.
c)
Spikes with a duration between 100 ns and 200 ns: (uncertainty region) hard
switching protection is activated, but also anti-saturation protection can be
activated, which may result in a sort of early activation of hard switching protection
or retarded activation of anti-saturation protection (in this case the saturation of the
choke won’t be deep).
d)
Spikes with a duration longer than 200 ns: (ASP region) anti-saturation protection
will certainly be activated at the first event.
HBCS
OUT pin
Good
working
Saturating
slightly
Capacitive
mode
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