
50
Am29LV652D
24961A5 May 5, 2006
D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90
°
C, V
CC
= 3.0 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 10, on page 30
for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note:
Includes all connections except V
CC
. Test conditions: V
CC
= 3.0 V, one connection at a time.
INPUT/OUTPUT CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
1.6
15
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
205
sec
Byte Program Time
5
150
μs
Excludes system level
overhead (Note 5)
Accelerated Byte Program Time
4
120
μs
Chip Program Time (Note 3)
42
126
sec
Description
Min
Max
Input voltage with respect to V
SS
on all device connections (including
A9, OE#, and RESET#) except I/Os
–1.0 V
12.5 V
Input voltage with respect to V
SS
on all I/Os
–1.0 V
V
CC
+ 1.0 V
V
CC
Current
–100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
12
16
pF
C
OUT
Output Capacitance
V
OUT
= 0
12
16
pF
C
E
/C
E2
Control Pin Capacitance
V
IN
= 0
6
8
pF
Parameter Description
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
°
C
10
Years
125
°
C
20
Years