
SDRAM Access
5-11
5.4.1 Host Reads/Writes
For host/SDRAM read/writes, the host loads a 19-bit address into the
Host SDRAM Target Address (
page 4-60) for writes and the Host
SDRAM Source Address (
page 4-61) for reads. These addresses are
written as if they are the upper 19 bits of a 21-bit SDRAM address. The
most signicant bit asserts either CS or CS1 to select one of the SDRAM
chips. The remaining bits are converted to row and column addresses by
the Memory Interface. Since the internal data bus of the L64021 is 64
bits wide, the SDRAM is set up to transfer a block of four, 16-bit words
at each access. It does so by setting the two least signicant column
address bits to 00 to start and then incrementing them to transfer the four
words.
The host has access to two 8-bit registers for SDRAM transfers, the Host
SDRAM Write Data register (
page 4-60) and the Host SDRAM Read
Data register
(page 4-59). The host can transfer the 8-byte data block
through the registers in big or little endian order by setting or clearing the
Host SDRAM Transfer Byte Ordering bit in Register 193
(page 4-59). The
L64021 operates in big endian mode, i.e., byte 0 occupies the upper bits
of the word and byte 8 occupies the lower bits.
The transfers are paced by the FIFO status bits in Register 192
(page 4-56). The host must read the status bits before writing or reading
the next 8 bytes to or from the data registers and before starting a new
transfer.
5.4.1.1 Host Read
The host read mode uses the SDRAM Source Address (Registers 199
through 201) as the SDRAM pointer for reading. This address is
autoincremented after a word is loaded from SDRAM into the on-chip
FIFO.
Figure 5.8 shows the ow for host reads from and writes to SDRAM. The
host begins a SDRAM read operation by setting or clearing the Host
SDRAM Byte Ordering bit (if necessary) to change the endian mode and
then writing the Host SDRAM Source Address. Typically, the Host
SDRAM Byte Ordering bit is set or cleared by the host at initialization
and not changed again. When the host writes in the LSB of the source
address, the L64021 automatically resets the pointers of the host read
FIFO (
Figure 5.1) and begins to ll the FIFO with new data from the
source address.