
L5989D
Functional description
Doc ID 15778 Rev 3
13/51
Below follows a brief description of the main blocks:
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A voltage pre-regulator supplies the internal circuitry. The external 1.8 V voltage
reference is supplied by this regulator.
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A voltage monitor circuit that checks the input and internal voltages
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A fully integrated sawtooth oscillator whose frequency is 400 kHz ± 10% when the Fsw
pin is floating. Its frequency can be increased/decreased connecting a proper resistor
to GND or VREF
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The internal current limitation circuitry monitors the current flowing in both embedded
switches to guarantee an effective protection even in extreme duty cycle conditions
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The over voltage protection (OVP) monitors the feedback voltage. If the voltage of this
pin overcomes the 20% of the internal reference value (600 mV ± 1%) it will force the
conduction of the low side switch until the overshoot is present
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A voltage mode amplifier. The inverting input and the output are externally available for
compensation
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A pulse width modulator (PWM) comparator and the relative logic to drive the
embedded switches
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The soft-start circuit charges an external capacitor with a constant current equal to
20 A (typ.). The soft-start feature is realized clamping the output of the error amplifier
until the voltage across the capacitor is below 2.7 V
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The PGOOD is an open collector output: low impedance if the feedback voltage is
lower than 0.85 times the internal reference of the error amplifier. An hysteresis is
provided
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The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter
and the decoding logic. It recognizes eight different voltage windows of a VREF voltage
magnitude for selecting additional features.
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An inhibit block for stand-by operation
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A circuit to realize the thermal protection function
5.1
Multifunction pin
The UOS pin is used to configure the device additional features accordingly to the voltage
bias imposed through VREF voltage partitioning.
The selectable options are:
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UVLO level: two pre-defined the under voltage lock out thresholds can be selected to
match the 3.3 V and 5 V or 12 V power bus
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SINK capability: this feature is always disabled during the soft-start period to be
compatible with pre-biased output voltages. After the soft-start phase, the synchronous
rectification can be enabled or not depending on the status of the UOS pin. Anyway, in
case an overvoltage is detected, the sink capability is always enabled to bring the FB
back to regulation as fast as possible
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OVP management: in case the latched mode is selected and an overvoltage event
recurs, the switching activity will be suspended until VCC is reapplied or the SS/INH pin
is toggled. Otherwise when the overvoltage transient is ended the regulator will work
accordingly to the load request without regulation discontinuity
The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter and
the decoding logic.
Table 5 shows the internal thresholds of each voltage window