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參數(shù)資料
| 型號： | L5953 |
| 廠商： | 意法半導體 |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | MULTIPLE SWITCHING VOLTAGE REGULATOR |
| 中文描述： | 多重開關(guān)穩(wěn)壓 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 217K |
| 代理商： | L5953 |
13/24
L5953
SPI INTERFACE
Signals Description (Figure 10)
The SPI interface available inside L5953 is able to work both in Mode 0 and Mode 3.
Serial Output (Q).
The output pin is used to transfer data serially out of the L5953. Data is shifted out on the
falling edge of the serial clock.
Serial Input (D).
The input pin is used to transfer data serially into the device. It receives instructions, address-
es, and data to be written. Input is latched on the rising edge of the serial clock.
Serial Clock (C)
. The serial clock provides the timing of the serial interface. Instructions, addresses, or data
present at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes after
the falling edge of the clock input.
Chip Select (S).
This input is used to select the L5953. The chip is selected by a high to low transition on the
S pin. At any time, the chip is deselected by a low to high transition on the S pin. As soon as the chip is dese-
lected, the Q pin is at high impedance state. The pin allows multiple L5953 to share the same SPI bus. After
power up, the chip is at the deselect state.
SPI Input/Output are supplied by an external supply voltage VSPI while the core is supplied by the stand-by
regulator VSTBY. The SPI is resetted by an internal signal whose buffered version is RES .
OPERATIONS
All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on
the first rising edge of clock (C) after the chip select (S) goes low. Prior to any operation, a one-byte instruction
code must be entered in the chip. This code is entered in the chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been
previously selected (S = low). Table 1 shows the instruction set and format for device operation. An invalid in-
struction (one not contained in table 1) leaves the chip as previously selected.
Write Enable (WREN and Write Disable (WRDI)
The L5953 contains a write enable latch. This latch must be set prior to every WRITE operation. The WREN
instruction will set the latch and the WRDI istruction will reset the latch. The latch is reset under all the following
conditions:
– Power on
– WRDI instruction executed
As soon as the WREN or WRDI instruction is received by the L5953, the circuit executes the instruction and
enters a wait mode until it is deselected.
Table 1. Instruction Set.
Instruction
Description
Instruction Format
WREN
Set Write Enable Latch
00000110
WRDI
Reset Write Enable Latch
00000100
WSTA
Write Status Register
00000010
RDIA
Read Diagnostic Register
00000101
RSTA
Read Status Register
00000011
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