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參數(shù)資料
| 型號： | L4992 |
| 廠商： | 意法半導體 |
| 英文描述： | TRIPLE OUTPUT POWER SUPPLY CONTROLLER |
| 中文描述： | 三路輸出電源控制器 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 296K |
| 代理商： | L4992 |
offered by manufacturer, also for surface mount assemblies.
+3.3 V Transformer
The primary winding carries the secondary power as well, thus the total primary average current is:
I
tot3
=
I
out3
+
V
inlin
I
out12
3.3
where V
inlin
is the voltage generated during the recirculation of the primary and fed into the input of the
+12V linear regulator. The turns ratio 1:n of the transformer is chosen so that V
inlin
is above 13V. To re-
duce the turns ratio in order to minimize stray parameters, the secondary is referred to the 3.3V output,
and therefore the minimum value is given by:
n
min
=
V
inlin
3.3
+
V
f
3.3
where V
f
is the forward drop across the rectifier (assume 1V to be conservative). Make sure the secon-
dary is connected with the proper polarity (see fig. 6).
The minimum primary inductance value can be expressed as:
L
3pmin
=
3
4
3.3
(
V
in
3.3
)
2
V
in
f
sw
[I
tot3
RF
(
V
in
3.3
)
n
V
in
I
out12
]
where RF, to get positive values for L
3pmin
, must satisfy the inequality:
RF
>
n
V
in
I
out12
I
tot3
(
V
in
3.3
)
and where V
in
can be either V
inmin
or V
inmax
, whichever gives the higher value for L
3pmin
.
With a primary inductance L
3p
> L
3pmin
the primary peak current, which must not saturate the magnetic
core, will be:
I
L3pk
=
I
tot3
+
3.3
(
V
in max
3.3
)
2
f
sw
L
3p
V
in max
+
n
I
out12
As to the transformer realization, the considerations regarding to the +5.1V inductor can be here repeated.
Power MOSFET’s and Schottky diodes
Since the gate drivers of the L4992 are powered by a 5V bus , the use of logic-level MOSFET’s is highly
recommended, especially for high current applications. Their breakdown voltage V
(BR)DSS
must be
greater than V
inmax
with a certain margin, so the selection will address 20V or 30V devices.
The R
DS(ON)
can be selected once the allowable power dissipation has been established. By selecting
identical power MOSFET’s as the main switch and the synchronous rectifier, the total power they dissi-
pate does not depend on the duty cycle. Thus, if P
ON
is this power loss (few percent of the rated output
power), the required R
DS(ON)
(@ 25 °C) can be derived from:
R
DS
(
ON
)
=
P
ON
I
out
2
(
1
+
α
T
)
where I
out
is either I
tot3
or I
out5
, according to the section under consideration,
α
is the temperature coeffi-
cient of R
DS(ON)
(typically,
α
= 5
10
-3
°C
-1
for these low-voltage classes) and
T the admitted tempera-
ture rise.
It is worth noticing, however, that generally the lower R
DS(ON)
, the higher is the gate charge Q
g
, which
leads to a higher gate drive consumption. In fact, each switching cycle, a charge Q
g
moves from the in-
put source to ground, resulting in an equivalent drive current:
I
g
=
Q
g
f
sw
DESIGN PROCEDURE
(continued)
L4992
14/26
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