參數(shù)資料
型號(hào)： L4990D
廠商： 意法半導(dǎo)體
英文描述： PRIMARY CONTROLLER
中文描述： 主控制器
文件頁(yè)數(shù)： 13/24頁(yè)
文件大小： 322K
代理商： L4990D
V
13pk
=
I
Qpk
R
sense
=(
V
COMP
1.4
)
3
(
8
)
the conductionof the switch is terminated.
To increase the noise immunity, a ”Leading Edge
Blanking” of about 100ns is internally realized as
shown in fig. 27. Because of that, the smoothing
RC filter between this pin and R
sense
could be re-
movedor, at least,considerablyreduced.
+
-
I
D97IN503
ISEN
0
3V
CLK
2V
+
-
+
-
1.2V
FROM E/A
OVERCURRENT
COMPARATOR
PWM
COMPARATOR
TO
PWM
LOGIC
TO
FAULT
LOGIC
13
Figure 27. Internal LEB
Pin 14.
DIS (Device Disable). When the voltage
on pin 14 rises above 2.5V the IC is shut down
and it is necessary to pull VCC (IC supply volt-
age, pin 8) below the UVLO threshold to allow the
device to restart. When disabled, the current con-
sumption of the IC is as low as beforestart-up.
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
28. It is also possible to realize an overvoltage
protection, as shown in the section ” Application
Ideas”.
If used, bypass this pin to ground with a filter ca-
pacitor to avoid spurious activation due to noise
spikes. If not, it is advisable to connect the pin to
SGND, even though it might be leftfloating.
Pin 15.
DC-LIM (Maximum Duty Cycle Limit). The
upper extreme, Dx, of the duty cycle range de-
pends on the voltage applied to this pin. Approxi-
mately,
D
x
R
T
R
T
+
230
(
9
)
if DC-LIM is grounded or left floating. Instead,
connecting DC-LIM to VREF (half duty cycle op-
tion),Dx will be set approximately to:
D
x
R
T
2
R
T
+
260
(
10
)
and the output switching frequency will be halved
with respect to the oscillator one because an in-
ternal T flip-flop (see block diagram, fig. 1) is acti-
vated.Fig. 29 shows the operation.
The half duty cycle option speeds up the dis-
charge of the timing capacitor C
T
(in order to get
duty cycles as close as possible to 50%) so the
oscillator frequency - with the same R
T
and C
T
-
will be slightly higher.
The halving of frequency can be used to reduce
losses at light load in all those systems that must
comply with requirements regarding energy con-
sumption (e.g.monitor displays).
+
-
C
D97IN502
DIS
D
R
Q
DISABLE
UVLO
2.5V
14
DISABLE
SIGNAL
Figure28. Disable (Latched)
L4990 - L4990A
13/24
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