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參數(shù)資料
| 型號(hào)： | L4990D |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | PRIMARY CONTROLLER |
| 中文描述： | 主控制器 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 322K |
| 代理商： | L4990D |
The frequency can be established with the aid of
fig. 13 diagrams or considering the approximate
relationship:
f
osc
1
C
T
(
0.693
R
T
+
K
T
)
(
1
)
where K
T
is defined as:
K
T
=
90, V
15
=
VREF
160 V
15
=
GND/OPEN
(
2
)
and is linked to the duration of the falling edge of
the sawtooth:
T
d
30
10
-9
+ K
T
C
T
(3)
T
d
is also the duration of the sync pulses deliv-
ered at pin 1 and defines the upper extreme of
the duty cycle range, D
x
(seepin 15 for D
x
defini-
tionand calculation).
In case V
15
is connected to VREF, however, the
switching frequency of the system will be as
high as half f
osc
.
If the IC is to be synchronizedto an externaloscil-
lator, R
T
and C
T
should be selected for a f
osc
lower than the master frequency in any condition
(typically, 10-20% ), depending on the tolerance
of R
T
and C
T
itself.
Pin 3.
DC (Duty Cycle Control). By biasing this
pin with a voltagebetween 1 and 3 V it is possible
to set the maximum duty cycle between 0 and the
upper extreme D
x
(seepin 15).
If D
max
is the desired maximum duty cycle, the
voltage V3 to be appliedto pin 3 is:
V
3
= 5 - 2
(2-Dmax)
(4)
D
max
is determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 22),
thus in case the device is synchronized to an ex-
ternal frequency f
ext
(and therefore the oscillator
amplitude is reduced),(4) changesinto:
V
3
=
5
4
exp
D
max
R
T
C
T
f
ext
(5)
A voltage below 1V will inhibit the driver output
stage. This could be used for a not-latcheddevice
disable, for example in case of overvoltage pro-
tection (seeapplication ideas).
If no limitation on the maximum duty cycle is re-
quired (i.e. D
MAX
= D
X
), the pin has to be left float-
ing. An internal pull-up holds the voltage above
3V. Shouldthe pin pick up noise (e.g. during ESD
tests), it can be connected to V
REF
through a
4.7k
resistor.
Pin 4.
VREF (Reference Voltage). An internal
generatorfurnishes an accuratevoltage reference
(5V
±
1.5%) that can be used to supply an external
circuit (consider someten mA).
A small film capacitor (1
μ
F typ.), connected be-
tween this pin and SGND, is recommended to
preventswitchingnoisefromaffectingthereference.
Beforedeviceturn-on,this pin has a sink current ca-
pabilityof 0.5mA.
Pin 5.
VFB (Error Amplifier Inverting Input). The
feedback signal is applied to this pin and is com-
pared to the E/A internal reference (2.5V). The
E/A output generates the control voltage which
fixesthe dutycycle.
The E/A features high gain-bandwidth product,
which allows to broaden the bandwidth of the
overall control loop, high slew-rate and current
capability, which improves its large signal behav-
ior. Usually the compensationnetwork, which sta-
bilizes the overall control loop, is connected be-
tween this pin and COMP (pin 6).
Pin 6.
COMP (Error Amplifier Output). Usually,
this pin is used for frequency compensation and
the relevant network is connected between this
pin and VFB (pin 5). Compensation networks to-
wards ground are not possible since the L4990
E/A is a voltage mode amplifier (low output im-
pedance). See application ideas for some exam-
ple of compensationtechniques.
Pin 7.
SS (Soft-Start). At device start-up, a ca-
pacitor (Css) connected between this pin and
SGND (pin 12) is charged by an internal current
generator, ISSC, up to about 7V. During this
ramp, the E/A output is clamped by the voltage
across Css itself and allowed to rise linearly, start-
ing from zero, up to the steady-state value im-
posed by the control loop. The maximum time in-
tervalduring which the E/A is clamped,referred to
as soft-starttime, is approximately:
+
-
R2
R1
R
T
C
T
D97IN501A
V
REF
RCT
DC
TO PWM LOGIC
4
3
2
Figure22. Duty cycle control.
L4990 - L4990A
10/24
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